Pulse output circuit, display device, and electronic device

ABSTRACT

An object of the present invention is to suppress deterioration in the thin film transistor. A plurality of pulse output circuits each include first to eleventh thin film transistors is formed. The pulse output circuit is operated on the basis of a plurality of clock signals which control each transistor, the previous stage signal input from a pulse output circuit in the previous stage, the next stage signal input from a pulse output circuit in the next stage, and a reset signal. In addition, a microcrystalline semiconductor is used for a semiconductor layer serving as a channel region of each transistor. Therefore, degradation of characteristics of the transistor can be suppressed.

BACKGROUND OF THE INVENTION 1. Field of the Invention

This invention relates to a driver circuit, a display device including adriver circuit formed over a common substrate with a pixel portion, oran electronic device including the display device.

2. Description of the Related Art

With the widespread use of large display devices such as liquid crystaltelevisions, display devices are required to be higher-value-added andthus under development. Particularly, a technique to configure a drivercircuit such as a gate driver over a common substrate with a pixelportion using thin film transistors (TFTs) whose channel region is madefrom an amorphous semiconductor is actively developed because thetechnique helps a reduction in cost and an improvement in reliability alot.

A thin film transistor whose channel region is formed from an amorphoussemiconductor causes deterioration such as an increase in thresholdvoltage or a decrease in field-effect mobility. If deterioration in thethin film transistor proceeds, there arises a problem such that a drivercircuit may have difficulty in operation and may fail to display animage. Therefore, a shift register capable of suppressing deteriorationin a transistor is disclosed in Patent Document 1. In the PatentDocument 1, in order to suppress degradation of transistorcharacteristics, two transistors are provided and the transistors areconnected between an output terminal of a flip-flop and a wiring towhich a low-voltage power supply potential VSS is supplied. Thus, thetransistors become conducting in turn. In such a manner, a period duringwhich each of the transistors is conducting can be shortened byapproximately half in a frame period; therefore, degradation oftransistor characteristics of the transistors can be suppressed to someextent.

REFERENCE

[Patent Document 1] Japanese Published Patent Application No.2005-050502

SUMMARY OF THE INVENTION

An object of an embodiment of the invention is to provide a derivercircuit and a display device which can suppress degradation ofcharacteristics of a thin film transistor.

One embodiment of the invention is a driver circuit including aplurality of pulse output circuits. Each of the plurality of pulseoutput circuits includes a first thin film transistor to an elevenththin film transistor. Each of the plurality of pulse output circuits iselectrically connected to a first signal line to a seventh signal line,a first power supply line to a second power supply line. As for thefirst thin film transistor, a first terminal is electrically connectedto the first power supply line, a second terminal is electricallyconnected to a gate of the third thin film transistor, a gate of thefourth thin film transistor, a gate of the fifth thin film transistor, asecond terminal of the ninth thin film transistor, and a first terminalof the tenth thin film transistor, and a gate is electrically connectedto the second signal line. As for the second thin film transistor, afirst terminal is electrically connected to a first terminal of thethird thin film transistor and a second terminal of the eighth thin filmtransistor, a second terminal is electrically connected to a gate of thesixth thin film transistor and a gate of the seventh thin filmtransistor, and a gate is electrically connected to the first powersupply line. As for the third thin film transistor, the first terminalis electrically connected to a first terminal of the second thin filmtransistor and the second terminal of the eighth thin film transistor, asecond terminal is electrically connected to the second power supplyline, and the gate is electrically connected to the second terminal ofthe first thin film transistor, the gate of the fourth thin filmtransistor, the gate of the fifth thin film transistor, the secondterminal of the ninth thin film transistor and the first terminal of thetenth thin film transistor. As for the fourth thin film transistor, afirst terminal is electrically connected to the seventh signal line anda second terminal of the sixth thin film transistor, a second terminalis electrically connected to the second power supply line, and the gateis electrically connected to the second terminal of the first thin filmtransistor, the gate of the third thin film transistor, the gate of thefifth thin film transistor, the second terminal of the ninth thin filmtransistor and the first terminal of the tenth thin film transistor. Asfor the fifth thin film transistor, a first terminal is electricallyconnected to the sixth signal line, a second terminal of the sevenththin film transistor and a first terminal of the eleventh thin filmtransistor, a second terminal is electrically connected to the secondpower supply line, and the gate is electrically connected to the secondterminal of the first thin film transistor, the gate of the third thinfilm transistor, the gate of the fourth thin film transistor, the secondterminal of the ninth thin film transistor and the first terminal of thetenth thin film transistor. As for the sixth thin film transistor, afirst terminal is electrically connected to the first signal line, thesecond terminal is electrically connected to the seventh signal line andthe first terminal of the fourth thin film transistor, and the gate iselectrically connected to the second terminal of the second thin filmtransistor and the gate of the seventh thin film transistor. As for theseventh thin film transistor, a first terminal is electrically connectedto the first signal line, the second terminal is electrically connectedto the sixth signal line, the first terminal of the fifth thin filmtransistor, and the first terminal of the eleventh thin film transistor,and the gate is electrically connected to the second terminal of thesecond thin film transistor and the gate of the sixth thin filmtransistor. As for the eighth thin film transistor, a first terminal iselectrically connected to the first power supply line, the secondterminal is electrically connected to the first terminal of the secondthin film transistor and the first terminal of the third thin filmtransistor, and a gate is electrically connected to the fourth signalline. As for the ninth thin film transistor, a first terminal iselectrically connected to the first power supply line, the secondterminal is electrically connected to a second terminal of the firstthin film transistor, the gate of the third thin film transistor, thegate of the fourth thin film transistor, the gate of the fifth thin filmtransistor, and the first terminal of the tenth thin film transistor,and a gate is electrically connected to the fifth signal line. As forthe tenth thin film transistor, the first terminal is electricallyconnected to the second terminal of the first thin film transistor, thegate of the third thin film transistor, the gate of the fourth thin filmtransistor, the gate of the fifth thin film transistor, and the secondterminal of the ninth thin film transistor, a second terminal iselectrically connected to the second power supply line, and a gate iselectrically connected to the fourth signal line. As for the elevenththin film transistor, a first terminal is electrically connected to thesixth signal line, the first terminal of the fifth thin film transistor,and the second terminal of the seventh thin film transistor, a secondterminal is electrically connected to the second power supply line, anda gate is electrically connected to the third signal line.

One embodiment of the invention is a driver circuit including aplurality of pulse output circuits. Each of the plurality of pulseoutput circuits includes a first thin film transistor to an elevenththin film transistor. Each of the plurality of pulse output circuits iselectrically connected to a first signal line to a seventh signal line,a first power supply line, a second power supply line, and a third powersupply line. As for the first thin film transistor, a first terminal iselectrically connected to the first power supply line, a second terminalis electrically connected to a gate of the third thin film transistor, agate of the fourth thin film transistor, a gate of the fifth thin filmtransistor, a second terminal of the ninth thin film transistor, and afirst terminal of the tenth thin film transistor, and a gate iselectrically connected to the second signal line. As for the second thinfilm transistor, a first terminal is electrically connected to a firstterminal of the third thin film transistor and a second terminal of theeighth thin film transistor, a second terminal is electrically connectedto a gate of the sixth thin film transistor and a gate of the sevenththin film transistor, and a gate is electrically connected to the thirdpower supply line. As for the third thin film transistor, the firstterminal is electrically connected to a first terminal of the secondthin film transistor and the second terminal of the eighth thin filmtransistor, a second terminal is electrically connected to the secondpower supply line, and the gate is electrically connected to the secondterminal of the first thin film transistor, the gate of the fourth thinfilm transistor, the gate of the fifth thin film transistor, the secondterminal of the ninth thin film transistor and the first terminal of thetenth thin film transistor. As for the fourth thin film transistor, afirst terminal is electrically connected to the seventh signal line anda second terminal of the sixth thin film transistor, a second terminalis electrically connected to the second power supply line, and the gateis electrically connected to the second terminal of the first thin filmtransistor, the gate of the third thin film transistor, the gate of thefifth thin film transistor, the second terminal of the ninth thin filmtransistor and the first terminal of the tenth thin film transistor. Asfor the fifth thin film transistor, a first terminal is electricallyconnected to the sixth signal line, a second terminal of the sevenththin film transistor and a first terminal of the eleventh thin filmtransistor, a second terminal is electrically connected to the secondpower supply line, and the gate is electrically connected to the secondterminal of the first thin film transistor, the gate of the third thinfilm transistor, the gate of the fourth thin film transistor, the secondterminal of the ninth thin film transistor and the first terminal of thetenth thin film transistor. As for the sixth thin film transistor, afirst terminal is electrically connected to the first signal line, thesecond terminal is electrically connected to the seventh signal line andthe first terminal of the fourth thin film transistor, and the gate iselectrically connected to the second terminal of the second thin filmtransistor and the gate of the seventh thin film transistor. As for theseventh thin film transistor, a first terminal is electrically connectedto the first signal line, the second terminal is electrically connectedto the sixth signal line, the first terminal of the fifth thin filmtransistor, and the first terminal of the eleventh thin film transistor,and the gate is electrically connected to the second terminal of thesecond thin film transistor and the gate of the sixth thin filmtransistor. As for the eighth thin film transistor, a first terminal iselectrically connected to the first power supply line, the secondterminal is electrically connected to the first terminal of the secondthin film transistor and the first terminal of the third thin filmtransistor, and a gate is electrically connected to the fourth signalline. As for the ninth thin film transistor, a first terminal iselectrically connected to the first power supply line, the secondterminal is electrically connected to a second terminal of the firstthin film transistor, the gate of the third thin film transistor, thegate of the fourth thin film transistor, the gate of the fifth thin filmtransistor, and the first terminal of the tenth thin film transistor,and a gate is electrically connected to the fifth signal line. As forthe tenth thin film transistor, the first terminal is electricallyconnected to the second terminal of the first thin film transistor, thegate of the third thin film transistor, the gate of the fourth thin filmtransistor, the gate of the fifth thin film transistor, and the secondterminal of the ninth thin film transistor, a second terminal iselectrically connected to the second power supply line, and a gate iselectrically connected to the fourth signal line. As for the elevenththin film transistor, a first terminal is electrically connected to thesixth signal line, the first terminal of the fifth thin film transistor,and the second terminal of the seventh thin film transistor, a secondterminal is electrically connected to the second power supply line, anda gate is electrically connected to the third signal line.

In the driver circuit, a reset signal may be supplied to the secondsignal line, the previous stage signal may be supplied to the fourthsignal line, the next stage signal may be supplied to the fifth signalline, and a first output signal and a second output signal mayrespectively be output from the sixth signal line and the seventh signalline. A clock signal may be supplied to the first signal line of each ofthe plurality of pulse output circuits in odd-numbered stages and aninverted clock signal may be supplied to the third signal line of eachof the plurality of pulse output circuits in odd-numbered stages. Theinverted clock signal may be supplied to the first signal line of eachof the plurality of pulse output circuits in even-numbered stages andthe clock signal may be supplied to the third signal line of each of theplurality of pulse output circuits in even-numbered stages.

In the driver circuit, the inverted clock signal may be delayed from theclock signal by half of a cycle.

In the driver circuit, the reset signal may be supplied to the secondsignal line, the previous stage signal may be supplied to the fourthsignal line, the next stage signal may be supplied to the fifth signalline, and the first output signal and the second output signal mayrespectively be output from the sixth signal line and the seventh signalline. A first clock signal may be supplied to the first signal line ofeach of the plurality of pulse output circuits in (J−3)th stage (J ispreferably a multiple of 4 which is 4 or more) and a second clock signalmay be supplied to the third signal line of each of the plurality ofpulse output circuits in (J−3)th stage. The second clock signal may besupplied to the first signal line of each of the plurality of pulseoutput circuits in (J−2)th stage and the third clock signal may besupplied to the third signal line of each of the plurality of pulseoutput circuits in (J−2)th stage. The third clock signal may be suppliedto the first signal line of each of the plurality of pulse outputcircuits in (J−1)th stage and the fourth clock signal may be supplied tothe third signal line of each of the plurality of pulse output circuitsin (J−1)th stage. The fourth clock signal may be supplied to the firstsignal line of each of the plurality of pulse output circuits in J-thstage and the first clock signal may be supplied to the third signalline of each of the plurality of pulse output circuits in J-th stage.

In the driver circuit, the fourth clock signal may be delayed from thethird clock signal by a fourth of a cycle, the third clock signal may bedelayed from the second clock signal by a fourth of a cycle, the secondclock signal may be delayed from the first clock signal by a fourth of acycle, the first clock signal may be delayed from the fourth clocksignal by a fourth of a cycle.

The driver circuit may include a capacitor. One electrode iselectrically connected to a second terminal of the first thin filmtransistor, the gate of the third thin film transistor, the gate of thefourth thin film transistor, the gate of the fifth thin film transistor,a second terminal of the thin film transistor, and the first terminal ofthe tenth thin film transistor. The other electrode is electricallyconnected to the second power supply line.

The driver circuit may include a twelfth thin film transistor. A firstterminal is electrically connected to the second terminal of the firstthin film transistor, the gate of the third thin film transistor, thegate of the fourth thin film transistor, the gate of the fifth thin filmtransistor, the second terminal of the ninth thin film transistor, andthe first terminal of the tenth thin film transistor. A second terminalis electrically connected to the second power supply line. A gate iselectrically connected to the seventh signal line.

In the driver circuit, the first thin film transistor to the elevenththin film transistor may each include a microcrystalline silicon in achannel region.

According to one embodiment of the present invention, it is possible toprovide a driver circuit in which degradation of characteristics of thethin film transistor can be suppressed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1D are circuit diagrams of a driver circuit;

FIGS. 2A and 2B are a circuit diagram of a driver circuit and a timingchart for an explanation of operation of the driver circuit;

FIGS. 3A and 3B are schematic diagrams showing operation of a drivercircuit;

FIGS. 4A and 4B are schematic diagrams showing operation of a drivercircuit;

FIGS. 5A and 5B are schematic diagrams showing operation of a drivercircuit;

FIGS. 6A and 6B are circuit diagrams of a driver circuit;

FIGS. 7A to 7C are circuit diagrams of a driver circuit;

FIGS. 8A and 8B are a circuit diagram of a driver circuit and a timingchart for an explanation of operation of the driver circuit;

FIGS. 9A and 9B are schematic diagrams showing operation of a drivercircuit;

FIGS. 10A and 10B are schematic diagrams showing operation of a drivercircuit;

FIGS. 11A and 11B are schematic diagrams showing operation of a drivercircuit;

FIGS. 12A and 12B are block diagrams of a display device;

FIGS. 13A to 13D are block diagrams of a display device;

FIGS. 14A and 14B are a circuit diagram of a driver circuit and a timingchart for an explanation of an operation of the driver circuit;

FIGS. 15A to 15C are a circuit diagrams of a pixel and timing charts foran explanation of an operation of the pixel;

FIGS. 16A to 16C are circuit diagrams of a pixel;

FIG. 17 is a cross-sectional view showing a driver circuit;

FIGS. 18A and 18B are cross-sectional views showing a driver circuit;

FIG. 19 is a cross-sectional view showing a driver circuit;

FIGS. 20A to 20C are cross-sectional views showing a manufacturingmethod of a driver circuit;

FIGS. 21A to 21C are cross-sectional views showing a method formanufacturing a driver circuit;

FIGS. 22A-1, 22A-2, 22B-1, and 22B-2 are diagrams showing multi-tonemasks applicable to a method for manufacturing a driver circuit;

FIGS. 23A to 23C are cross-sectional views showing a method formanufacturing a driver circuit;

FIGS. 24A and 24B are cross-sectional views showing a method formanufacturing a driver circuit;

FIGS. 25A to 25C are cross-sectional views showing a method formanufacturing a driver circuit;

FIGS. 26A and 26B are a top view and a cross-sectional view showing adisplay device;

FIGS. 27A to 27D are diagrams showing electronic devices including adisplay device;

FIGS. 28A and 28B are circuit diagrams of a driver circuit;

FIG. 29 is a circuit diagram of a driver circuit;

FIG. 30 is a circuit diagram of a driver circuit.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, embodiments of the present invention will be described withreference to the accompanying drawings. Note that the embodiments can beimplemented in many different modes, and it is to be easily understoodby those skilled in the art that modes and details of the presentinvention can be variously changed without departing from the spirit andthe scope of the present invention. Therefore, the present inventionshould not be construed as being limited to the description of thefollowing embodiments. Note that in structures described below,reference numerals denoting the same portions or portions having similarfunctions are used in common in different drawings, and detaileddescription thereof is not repeated.

Note that as for some components shown in some of the drawings, etc. forthe embodiments, the size, the layer thickness, and distortion in signalwaveforms are exaggerated for purposes of clarity and are thus notnecessarily limit the actual sizes of those components.

Note that the terms such as “first”, “second”, and “third” in thisspecification are used in order to avoid confusion between componentsand do not set a limitation on number.

Embodiment 1

In this embodiment, an embodiment of a driver circuit and a structure ofa thin film transistor are described.

First, a structure of the driver circuit is described. The drivercircuit in this embodiment can function as a shift register used for agate driver, a source driver, or a display device, for example.

A driver circuit which functions as a shift register is described withreference to FIGS. 1A to 1D, FIGS. 2A and 2B, FIGS. 3A and 3B, FIGS. 4Aand 4B, FIGS. 5A and 5B, FIGS. 6A and 6B, FIGS. 28A and 28B, and FIG.29. A shift register 100 includes first to N-th pulse output circuits101_1 to 101_N (N≥3) (see FIG. 1A). A clock signal CK, an inverted clocksignal CKB, and a reset signal RES are input respectively from a firstwiring 102, a second wiring 103, and a third wiring 104 to each of thefirst to N-th pulse output circuits 101_1 to 101_N in the shift register100 shown in FIG. 1A. A start pulse SP or a signal, referred to as theprevious stage signal Lin, which is from the pulse output circuit in theprevious stage, is input to the pulse output circuit in each stage. Inaddition, a signal, referred to as the next stage signal Rin, which isfrom the pulse output circuit in the next stage, is input to the pulseoutput circuit in each stage. The pulse output circuit in each stageoutputs a first output signal Gout to a gate line, a data line, etc. andoutputs a second output signal SRout to the pulse output circuit in theprevious and/or next stage. Note that the pulse output circuit in adummy stage for outputting a signal which does not affect display in adisplay portion may be provided. For example, in the structure where theplurality of pulse output circuits are used as a shift register in agate driver and output pulses sequentially to n gate lines, N stages(n≤N) may be provided.

Note that terminals to which the clock signal CK and the inverted clocksignal CKB are input are different between the odd-numbered stages andthe even-numbered stages of the plurality of pulse output circuits.Specifically, if the odd-numbered stages of the pulse output circuit101_1 has a structure as shown in FIG. 1B in which the clock signal CKis input to a first terminal, the reset signal RES is input to a secondterminal, the inverted clock signal CKB is input to a third terminal,the previous stage signal Lin is input to a fourth terminal, the nextstage signal Rin is input to a fifth terminal, a first output signalGout is output from a sixth terminal, and a second output signal SRoutis output from a seventh terminal, the even-numbered stages of the pulseoutput circuit 101_2 has a structure as shown in FIG. 1C in which theinverted clock signal CKB is input to a first terminal, the reset signalRES is input to a second terminal, the clock signal CK is input to athird terminal, the previous stage signal Lin is input to a fourthterminal, the next stage signal Rin is input to a fifth terminal, anoutput signal Gout is output from a sixth terminal, and a second outputsignal SRout is output from a seventh terminal. Note that the clocksignal CK and the inverted clock signal CKB become an H-level signal(high power supply potential level) and an L-level signal (low powersupply potential level) repeatedly at a regular interval. Here, theinverted clock signal is delayed from the clock signal CK by half of acycle.

Note that a voltage indicates a potential difference between a potentialand a reference potential (e.g., a ground potential) in many cases.Therefore, in this specification, a voltage and a potential can beinterchanged with each other for explanation.

Next, a specific example of the circuit structure of the pulse outputcircuit is described with reference to FIG. 1D. Note that in FIG. 1D, astructure of the pulse output circuit in the odd-numbered stage isdescribed as an example. Note that a difference between the plurality ofpulse output circuits in the odd-numbered stages and that in theeven-numbered stages is, as described above, in the terminals to whichthe clock signal CK and the inverted clock signal CKB are input.

The pulse output circuit includes a first thin film transistor 111 to aneleventh thin film transistor 121. In addition, FIG. 1D shows the casewhere a high-voltage power supply potential VDD is supplied through afirst power supply line 131 and a low-voltage power supply potential VSSis supplied through a second power supply line 132 besides the signalswhich are input to a first terminal to a seventh terminal. Note that inFIG. 1D, a wiring for inputting the clock signal CK to a first terminalis a first signal line 151, a wiring for inputting the reset signal RESto a second terminal is a second signal line 152, a wiring for inputtingthe inverted clock signal to a third terminal is a third signal line153, a wiring for inputting the previous stage signal Lin to a fourthterminal is a fourth signal line 154, a wiring for inputting the nextstage signal Rin to a fifth terminal is a fifth signal line 155, and awiring through which a sixth terminal outputs a first output signal Goutis a sixth signal line 156, a wiring through which a seventh terminaloutputs a second output signal SRout is a seventh signal line 157.

As for the first thin film transistor 111, a first terminal is connectedto the first power supply line 131, a second terminal is connected to agate of the third thin film transistor 113, a gate of the fourth thinfilm transistor 114, a gate of the fifth thin film transistor 115, asecond terminal of the ninth thin film transistor 119, and a firstterminal of the tenth thin film transistor 120, and a gate is connectedto the second signal line 152. As for the second thin film transistor112, a first terminal is connected to a first terminal of the third thinfilm transistor 113 and a second terminal of the eighth thin filmtransistor 118, a second terminal is connected to a gate of the sixththin film transistor 116 and a gate of the seventh thin film transistor117, and a gate is connected to the first power supply line 131. As forthe third thin film transistor 113, the first terminal is connected tothe first terminal of the second thin film transistor 112 and the secondterminal of the eighth thin film transistor 118, a second terminal isconnected to the second power supply line 132, and the gate is connectedto the second terminal of the first thin film transistor 111, the gateof the fourth thin film transistor 114, the gate of the fifth thin filmtransistor 115, the second terminal of the ninth thin film transistor119, and the first terminal of the tenth thin film transistor 120. Asfor the fourth thin film transistor 114, a first terminal is connectedto the seventh signal line 157 and a second terminal of the sixth thinfilm transistor 116, a second terminal is connected to the second powersupply line 132, and the gate is connected to the second terminal of thefirst thin film transistor 111, the gate of the third thin filmtransistor 113, the gate of the fifth thin film transistor 115, thesecond terminal of the ninth thin film transistor 119, and the firstterminal of the tenth thin film transistor 120. As for the fifth thinfilm transistor 115, a first terminal is connected to the sixth signalline 156, a second terminal of the seventh thin film transistor 117, anda first terminal of the eleventh thin film transistor 121, a secondterminal is connected to the second power supply line 132, and the gateis connected to the second terminal of the first thin film transistor111, the gate of the third thin film transistor 113, the gate of thefourth thin film transistor 114, the second terminal of the ninth thinfilm transistor 119, and the first terminal of the tenth thin filmtransistor 120. As for the sixth thin film transistor 116, a firstterminal is connected to the first signal line 151, the second terminalis connected to the seventh signal line 157 and the first terminal ofthe fourth thin film transistor 114, and the gate is connected to thesecond terminal of the second thin film transistor 112 and the gate ofthe seventh thin film transistor 117. As for the seventh thin filmtransistor 117, a first terminal is connected to the first signal line151, the second terminal is connected to the sixth signal line 156, thefirst terminal of the fifth thin film transistor 115, and the firstterminal of the eleventh thin film transistor 121, and the gate isconnected to the second terminal of the second thin film transistor 112and the gate of the sixth thin film transistor 116. As for the eighththin film transistor 118, a first terminal is connected to the firstpower supply line 131, the second terminal is connected to the firstterminal of the second thin film transistor 112 and the first terminalof the third thin film transistor 113, and a gate is connected to thefourth signal line 154. As for the ninth thin film transistor 119, afirst terminal is connected to the first power supply line 131, thesecond terminal is connected to a second terminal of the first thin filmtransistor 111, the gate of the third thin film transistor 113, the gateof the fourth thin film transistor 114, the gate of the fifth thin filmtransistor 115, and the first terminal of the tenth thin film transistor120, and a gate is connected to the fifth signal line 155. As for thetenth thin film transistor 120, the first terminal is connected to thesecond terminal of the first thin film transistor 111, the gate of thethird thin film transistor 113, the gate of the fourth thin filmtransistor 114, the gate of the fifth thin film transistor 115, and thesecond terminal of the ninth thin film transistor 119, a second terminalis connected to the second power supply line 132, and a gate isconnected to the fourth signal line 154. As for the eleventh thin filmtransistor 121, a first terminal is connected to the sixth signal line156, the first terminal of the fifth thin film transistor 115, and thesecond terminal of the seventh thin film transistor 117, a secondterminal is connected to the second power supply line 132, and a gate isconnected to the third signal line 153.

Note that between the gate and the second terminal of the sixth thinfilm transistor 116 and between the gate and the second terminal of theseventh thin film transistor 117, capacitors may additionally beprovided which perform a bootstrap operation by making each of the gatesof the sixth thin film transistor 116 and the seventh thin filmtransistor 117 in a floating state. Alternatively, if the bootstrapoperation can be realized by a gate capacity of the sixth thin filmtransistor 116 and a gate capacity of the seventh thin film transistor117, the capacitor can be removed.

Note that a thin film transistor is an element having at least threeterminals of a gate, a drain, and a source. The thin film transistor hasa channel region between a drain region and a source region, and currentcan flow through the drain region, the channel region, and the sourceregion. Here, since the source and the drain of the thin film transistormay interchange depending on the structure, the operating condition, andthe like of the thin film transistor, it is difficult to define which isa source or a drain. Thus, a region which serves as a source or a drainis not referred to as a source or a drain in some cases. In such a case,one of the source and the drain may be referred to as a first terminaland the other may be referred to as a second terminal, for example.Alternatively, one of the source and the drain may be referred to as afirst electrode and the other may be referred to as a second electrode,for example. Further alternatively, one of the source and the drain maybe referred to as a first region and the other may be referred to as asecond region, for example.

Note that a structure of a thin film transistor can employ various modeswithout being limited to a specific stricture. For example, a multi-gatestructure having two or more gate electrodes can be used.

As another example, a structure where gate electrodes are formed aboveand below a channel region can be used. Note that the structure wheregate electrodes are formed above and below a channel region issubstantially equivalent to a structure where a plurality of thin filmtransistors is connected in parallel.

A structure where a gate electrode is formed above a channel region, astructure where a gate electrode is formed below a channel region, astaggered structure, an inverted staggered structure, a structure wherea channel region is divided into a plurality of regions, or a structurewhere channel regions are connected in parallel or in series can beused. In addition, a structure where a source electrode or a drainelectrode overlaps with a channel region (or part thereof) can be used.

Note that when it is explicitly described that “A and B are connected”,the case where A and B are electrically connected, the case where A andB are functionally connected, and the case where A and B are directlyconnected are included therein. Here, each of A and B is an object(e.g., a device, an element, a circuit, a wiring, an electrode, aterminal, a conductive film, or a layer). Accordingly, another elementmay be interposed between elements having a connection relationillustrated in drawings and texts, without limitation to a predeterminedconnection relation, for example, the connection relation illustrated inthe drawings and the texts.

For example, in the case where A and B are electrically connected, oneor more elements which enable electrical connection between A and B(e.g., a switch, a thin film transistor, a capacitor, an inductor, aresistor, and/or a diode) may be connected between A and B.Alternatively, in the case where A and B are functionally connected, oneor more circuits which enable functional connection between A and B(e.g., a logic circuit such as an inverter, a NAND circuit, or a NORcircuit; a signal converter circuit such as a DA converter circuit, anAD converter circuit, or a gamma correction circuit; a potential levelconverter circuit such as a power supply circuit (e.g., a dc-dcconverter, a step-up dc-dc converter, or a step-down de-dc converter) ora level shifter circuit for changing a potential level of a signal; avoltage source; a current source; a switching circuit; an amplifiercircuit such as a circuit which can increase signal amplitude, theamount of current, or the like, an operational amplifier, a differentialamplifier circuit, a source follower circuit, or a buffer circuit; asignal generation circuit; a memory circuit; and/or a control circuit)may be connected between A and B. For example, in the case where asignal output from A is transmitted to B even when another circuit isinterposed between A and B, A and B are functionally connected.

Note that when it is explicitly described that “A and B are electricallyconnected”, the case where A and B are electrically connected (i.e., thecase where A and B are connected with another element or another circuitinterposed therebetween), the case where A and B are functionallyconnected (i.e., the case where A and B are functionally connected withanother circuit interposed therebetween), and the case where A and B aredirectly connected (i.e., the case where A and B are connected withoutanother element or another circuit interposed therebetween) are includedtherein. That is, when it is explicitly described that “A and B areelectrically connected”, the description is the same as the case whereit is explicitly only described that “A and B are connected”.

Note that a thin film transistor in this embodiment is a thin filmtransistor (TFT) formed using microcrystalline (also referred to asmicrocrystal, nanocrystal, or semi-amorphous) silicon for a channellayer. Therefore, a driver circuit can be made in which degradation ofcharacteristics of the thin film transistor can be suppressed.

Note that instead of being thin film transistors, the first to thirdthin film transistors and the eighth to eleventh thin film transistorsmay be switches turned into a conduction state (an on state) or anon-conduction state (an off state) depending on an input signal.

Note that a variety of switches can be used as a switch. For example, anelectrical switch, a mechanical switch, or the like can be used. Thatis, any element can be used as long as it can control a current flow,without limitation to a certain element. For example, a transistor(e.g., a bipolar transistor or a MOS transistor), a diode (e.g., a PNdiode, a PIN diode, a Schottky diode, an MIM (metal insulator metal)diode, an MIS (metal insulator semiconductor) diode, or adiode-connected transistor), or the like can be used as a switch.Alternatively, a logic circuit in which such elements are combined canbe used as a switch.

Next, operation of a shift register shown in FIGS. 1A to 1D is describedwith reference to FIGS. 2A and 2B, FIGS. 3A and 3B, FIGS. 4A and 4B,FIGS. 5A and 5B, and FIGS. 6A and 6B. For explanation, note that aconnection node of the second terminal of the second thin filmtransistor 112, the gate of the sixth thin film transistor 116, and thegate of the seventh thin film transistor 117 is a node A. Further, inorder to specifically describe the operation of the shift register, afirst period T1, a second period T2, a third period T3, a fourth periodT4, and a fifth period T5, which are shown in a timing chart in FIG. 2B,are separately explained. Note that in the following description, thefirst to eleventh thin film transistors 111 to 121 are N-channel thinfilm transistors and are in a conduction state when a gate-sourcevoltage Vgs exceeds a threshold voltage (Vth). Also note that in FIG.2B, the first to eleventh thin film transistors 111 to 121 serve as ashift register included in a gate driver, and a period 201 is a verticalretrace period and a period 202 is a gate selection period. Further, thetiming chart in FIG. 2B shows a specific example of the waveforms of theclock signal CK, the inverted clock signal CKB, the reset signal RES,the previous stage signal Lin, the next stage signal Rin, and secondoutput signal SRout of each of the stages (e.g., SRout1 of the firststage). Furthermore, a high power supply potential level and a low powersupply potential level of each of the signals are respectively VDD andVSS, except the node A. In addition, a first output signal Gout1 isomitted because it has a wave form same as the second output signalSRout1.

In the first period T1, the reset signal RES becomes an H-level signaland the first thin film transistor 111 whose gate is connected to thesecond signal line 152 are conducting. At the time, the clock signal CKis an H-level signal, and the inverted clock signal CKB, the previousstage signal Lin, and the next stage signal Rin are L-level signals. Asshown in FIG. 3A, the first thin film transistor 111 becomes conducting,and the second thin film transistor 112, the third thin film transistor113, the fourth thin film transistor 114, and the fifth thin filmtransistor 115 become conducting. Therefore, a current flows as shown bya dotted arrow in FIG. 3A, and a potential of each of the wirings in thefirst period T1 is determined as shown in FIG. 2B. That is, the firstperiod T is a period for reset of a potential of each of the wirings(i.e., for setting a potential at VSS) in the pulse output circuit. Inaddition, in the first period T1, the second output signal SRout1 is anL-level signal.

When the reset signal RES is input to the gate of the first thin filmtransistor 111 every vertical retrace period which is the period 201, anode of each of the thin film transistors can be set at a potential ofVDD or VSS. Therefore, a so-called dynamic circuit in this embodiment,which is driven with the use of a node in a floating state, each nodecan be reset, whereby the level of noise immunity and operationreliability can be improved to be equal to that of a static circuit.

Next, in the second period T2, the previous stage signal Lin is anH-level signal, and the eighth thin film transistor 118 and the tenththin film transistor 120 whose gates are each connected to the fourthsignal line 154 are thus conducting. At the time, the inverted clocksignal CKB is an H-level signal, and the clock signal CK, the resetsignal RES, and the next stage signal Rin are L-level signals. Further,at the time, the eighth thin film transistor 118 is conducting asillustrated in FIG. 3B. The second thin film transistor 112 areconducting as in the first period T1, and a current flows as shown by adotted arrow in FIG. 3B. At the time, the node A uses the secondterminal of the eighth thin film transistor 118 as the source;therefore, a potential of the node A becomes a value VDD-Vth where avalue of a threshold voltage Vth of the eighth thin film transistor 118is subtracted from a value of a potential of the first power supply line131. When the second terminal of the eighth thin film transistor 118 hasthe value VDD-Vth, the thin film transistor 118 is non-conducting andthe node A is in a floating state while maintaining the value VDD-Vth.Note that as shown in FIG. 3B, the sixth thin film transistor 116 andthe seventh thin film transistor 117 are conducting, but at the sametime, since the potential of the first signal line 151 is VSS, apotential of each of the wirings in the second period T2 is determinedas in FIG. 2B. That is, the second period T2 is a period where the nodeA in the pulse output circuit is in a floating state. In addition, inthe second period T2, the second output signal SRout1 is an L-levelsignal.

Next, in the third period T3, the clock signal CK becomes an H-levelsignal. At the time, the inverted clock signal CKB, the reset signalRES, the previous stage signal Lin, and the next stage signal Rin areL-level signals. Further, at the time, as shown in FIG. 4A, the sixththin film transistor 116 and the seventh thin film transistor 117 areconducting, that is, the sixth thin film transistor 116 and the sevenththin film transistor 117 are in a state where current flows between asource and a drain (as shown by a dotted arrow in FIG. 4A), and apotential of each second terminal (the source side) of the sixth thinfilm transistor 116 and the seventh thin film transistor 117 starts toincrease. There is a capacitive coupling due to parasitic capacitancebetween a gate and a source of each of the sixth thin film transistor116 and the seventh thin film transistor 117, so that a potential of thenode A in a floating state increases as a potential of the secondterminal serving as the source increases (bootstrap operation). Thepotential of the node A eventually becomes higher than VDD+Vth, and eachsecond terminal of the sixth thin film transistor 116 and the sevenththin film transistor 117 thus has a potential of VDD. Therefore, thesecond output signal SRout1 becomes an H-level signal in the thirdperiod T3, that is, a potential of the node A in a floating state isincreased by the bootstrap operation and the first output signal Gout1and the second output signal SRout1 are output as H-level signals. Then,the second output signal SRout1 is input as the previous stage signalLin to the pulse output circuit in a second stage.

Note that as shown in FIG. 1D, by providing the second thin filmtransistor 112 whose gate is supplied with the high-voltage power supplypotential VDD, advantages described below are obtained.

Without the second thin film transistor 112 whose gate is supplied withthe high-voltage power supply potential VDD, if a potential of the nodeA is raised by bootstrap operation, a potential of a source which is thesecond terminal of the eighth thin film transistor 118 increases to avalue higher than the high-voltage power supply potential VDD. Then, thefirst terminal of the eighth thin film transistor 118 comes to serve asa source thereof. Therefore, in the eighth thin film transistor 118, alarge bias voltage is applied and thus significant stress is appliedbetween a gate and a source and between a gate and a drain in the thirdperiod T3, which can cause deterioration in the thin film transistor.

If the second thin film transistor 112 is provided whose gate issupplied with high-voltage power supply potential VDD, a potential ofthe node A is raised by bootstrap operation, but at the same time, anincrease in a potential of the second terminal of the eighth thin filmtransistor 118 can be prevented. In other words, with the second thinfilm transistor 112, a negative bias voltage applied between a gate anda source of the eighth thin film transistor 118 can be reduced.Accordingly, with a circuit structure in this embodiment, a negativebias voltage applied between a gate and a source of the eighth thin filmtransistor 118 can be reduced, so that deterioration in the eighth thinfilm transistor 118, which is due to stress, can further be restrained.

Note that the second thin film transistor 112 is provided so as to beconnected, through the first terminal and the second terminal thereof,between the second terminal of the eighth thin film transistor 118 andthe gate of the sixth thin film transistor 116, or between the secondterminal of the eighth thin film transistor 118 and the gate of theseventh thin film transistor 117.

Note that since the high-voltage power supply potential VDD is appliedto the gate of the second thin film transistor 112, the second thin filmtransistor 112 is conducting in almost all the periods withoutapplication of a large amount of voltage between the gate and a sourcethereof. Therefore, when channel region of the thin film transistor isformed using an amorphous semiconductor, deterioration in the thin filmtransistor becomes pronounced, on the other hand, progress indeterioration can further be restrained with the use of microcrystallinesilicon, which is a typical example of a microcrystalline semiconductordescribed in this embodiment, for channel regions of each transistor.Note that with a multi-gate structure where two or more gate electrodesare provided, the second thin film transistor 112 can be redundant;thus, progress in the deterioration can further be restrained.

Note that although the gate of the second thin film transistor 112 issupplied with high-voltage power supply potential VDD in FIG. 1D, it isacceptable as long as the gate of the second thin film transistor 112 issupplied with a potential which brings the second thin film transistor112 into conduction. FIG. 28A shows an example of the structure wherethe gate of the second thin film transistor 112 is connected to a thirdpower supply line 2801 to which a conduction holding potential VCC whichbrings the second thin film transistor 112 into conduction is appliedand which is provided aside from the first power supply line 131 towhich the high-voltage power supply potential VDD is applied. Note thatit is acceptable as long as the conduction holding potential VCC is in amagnitude relation as follows: VSS<VCC≤VDD, and progress indeterioration in the second thin film transistor 112 can further berestrained in a manner that the conduction holding potential VCC is madesmaller in value than the high-voltage power supply potential VDD.

Alternatively, a structure may be used where a twelfth thin filmtransistor 2802 is added to the structure shown in FIG. 1D (see FIG.28B). As for the twelfth thin film transistor 2082, a first terminal isconnected to the second terminal of the first thin film transistor 111,the gate of the third thin film transistor 113, the gate of the fourththin film transistor 114, the gate of the fifth thin film transistor115, the second terminal of the ninth thin film transistor 119, and thefirst terminal of the tenth thin film transistor 120; a second terminalis connected to the second power supply line 132; and a gate isconnected to the seventh signal line 157. Note that the gate of thetwelfth thin film transistor 2802 may be connected to the sixth signalline 156. The twelfth thin film transistor 2802 is conducting when theseventh signal line 157 (or the sixth signal line 156) supplies anH-level signal. In other words, in the third period T3 where the seventhsignal line 157 (or the sixth signal line 156) supplies an H-levelsignal, a node to which the second terminal of the first thin filmtransistor 111, the gate of the third thin film transistor 113, the gateof the fourth thin film transistor 114, the gate of the fifth thin filmtransistor 115, the second terminal of the ninth thin film transistor119, and the first terminal of the tenth thin film transistor 120 areconnected, and the second power supply line 132 to which VSS is suppliedare made to be conducting; thus, it is possible to more reliably bringthe third thin film transistor 113, the fourth thin film transistor 114,and the fifth thin film transistor 115 out of conduction. Therefore,malfunction of the driver circuit can be reduced.

Next, in the fourth period T4, the next stage signal Rin (SRout_2 inFIG. 2B) obtained from the pulse output circuit in the second stagebecomes an H-level signal, and the ninth thin film transistor 119 whosegate is connected to the fifth signal line 155 is thus conducting. Atthe time, the inverted clock signal CKB is an H-level signal, and theclock signal CK, the reset signal RES, and the previous stage signal Linare L-level signals. The third thin film transistor 113, the fourth thinfilm transistor 114, the fifth thin film transistor 115, and theeleventh thin film transistor 121 are conducting. The second thin filmtransistor 112 is conducting as in the third period T3, and each gate ofthe sixth thin film transistor 116 and the seventh thin film transistor117 is set at VSS; thus, the sixth thin film transistor 116 and theseventh thin film transistor 117 are non-conducting. Therefore, acurrent flows as shown by a dotted arrow in FIG. 4B, and the potentialof each wiring in the fourth period T4 is thus determined as in FIG. 2B.That is, in the fourth period T4, the first output signal Gout1 and thesecond output signal SRout1 are output as L-level signals.

Then, the fifth period T5 is described as a period T5-1 and a periodT5-2. The polarities of the clock signal CK and the inverted clocksignal CKB are different between in the period T5-1 and the period T5-2.First, the period T5-1 is described. In the period T5-1, the clocksignal CK is an H-level signal, and the inverted clock signal CKB, thereset signal RES, the previous stage signal Lin, and the next stagesignal Rin are L-level signals. The first thin film transistor 111, theeighth thin film transistor 118, the ninth thin film transistor 119, andthe tenth thin film transistor 120 are non-conducting, and the gates ofthe third thin film transistor 113, the fourth thin film transistor 114,and the fifth thin film transistor 115 are kept in a floating state aswell as in the fourth period. That is, the third thin film transistor113, the fourth thin film transistor 114, and the fifth thin filmtransistor 115 are kept in a conduction state. Further, the second thinfilm transistor 112 is conducting as in the fourth period T4, and thegates of the sixth thin film transistor 116 and the seventh thin filmtransistor 117 are set at VSS; thus, the sixth thin film transistor 116and the seventh thin film transistor 117 are non-conducting.Furthermore, the eleventh thin film transistor 121 is conducting.Therefore, a current flows as shown by a dotted arrow in FIG. 5A, and apotential of each of the wirings in the period T5-1 is determined asshown in FIG. 5A. Next, in the period T5-2, the inverted clock signalCKB is an H-level signal, and the clock signal CK, the reset signal RES,the previous stage signal Lin, and the next stage signal Rin are L-levelsignals. As in the period T5-1, the first thin film transistor 111, theeighth thin film transistor 118, the ninth thin film transistor 119, andthe tenth thin film transistor 120 are non-conducting; thus, the gatesof the third thin film transistor 113, the fourth thin film transistor114, and the fifth thin film transistor 115 are kept in a floating stateas well as in the fourth period. That is, the third thin film transistor113, the fourth thin film transistor 114, and the fifth thin filmtransistor 115 are kept in a conduction state. Further, the second thinfilm transistor 112 is conducting as in the fourth period T4, and eachgate of the sixth thin film transistor 116 and the seventh thin filmtransistor 117 are set at VSS; thus, the sixth thin film transistor 116and the seventh thin film transistor 117 are non-conducting.Furthermore, the eleventh thin film transistor 121 is conducting.Therefore, a current flows as shown by a dotted arrow in FIG. 5B, andthe potentials of the wirings in the period T5-2 are determined as shownin FIG. 2B. That is, in the fifth period T5, the first output signalGout1 and the second output signal SRout1 are output as L-level signals.

Note that a structure can be alternatively used where a capacitor 2901is added to the structure shown in FIG. 1D (see FIG. 29). As for thecapacitor 2901, one electrode is connected to the second terminal of thefirst thin film transistor 111, the gate of the third thin filmtransistor 113, the gate of the fourth thin film transistor 114, thegate of the fifth thin film transistor 115, the second terminal of thethin film transistor 119, and the first terminal of the tenth thin filmtransistor 120; and the other electrode is connected to the second powersupply line 132. The capacitor 2901 holds a potential of a node to whichthe second terminal of the first thin film transistor 111, the gate ofthe third thin film transistor 113, the gate of the fourth thin filmtransistor 114, the gate of the fifth thin film transistor 115, thesecond terminal of the thin film transistor 119, and the first terminalof the tenth thin film transistor 120 are connected. That is, in thefifth period T5 where the seventh signal line 157 (or the sixth signalline) holds an L-level signal, the third thin film transistor 113, thefourth thin film transistor 114, and the fifth thin film transistor 115hold a potential which allows them to be conducting more reliably.Therefore, malfunction of the driver circuit can be reduced.

The shift register in this embodiment separately has the sixth signalline 156 and the seventh signal line 157, which respectively output thefirst output signal Gout and the second output signal SRout.Accordingly, the sixth thin film transistor and the seventh thin filmtransistor can differ in the size of the thin film transistor inresponse to the load on elements in the next stage of the sixth signalline 156 and the seventh signal line 157, and the delay in rising edgeof signals can be restrained. In this case, the size of the thin filmtransistor means a ratio of W/L (W: channel width, and L: channellength) of the thin film transistor. Note that as shown in FIG. 6A, thesixth signal line 156 and the seventh signal line 157 may be integratedinto the signal line 166 which outputs the first output signal Gout andthe second output signal SRout. Further, even if the eleventh thin filmtransistor is also removed at the same time, the same output signal canbe obtained. The sixth signal line 156 and the seventh signal line 157are integrated and the eleventh thin film transistor is removed; thus, areduction in the number of thin film transistors and in the number ofwirings to which the inverted clock signal is input can be achieved.Accordingly, a reduction in the size of the shift register can berealized.

Note that in the circuit structure of the pulse output circuit in thisembodiment, the eleventh thin film transistor 121 is provided. With theeleventh thin film transistor 121, the first output signal Gout of thesixth signal line 156 can have a shorter fall time. At the same time,there is no problem if the circuit structure of the pulse output circuitin this embodiment achieves the same operation as that shown in FIGS. 2Aand 2B, FIGS. 3A and 3B, FIGS. 4A and 4B, and FIGS. 5A and 5B. Forexample, as shown in drawings, a structure can be used where a pluralityof the first power supply lines 131 and/or the second power supply lines132 is provided, and a plurality of high-voltage power supply potentialsand/or low-voltage power supply potentials is supplied. For example, asshown in FIG. 6B, a wiring serving as the first power supply line may bedivided into a plurality of lines, a power supply line 171 and a powersupply line 172, which respectively supply a first high-voltage powersupply potential VDD1 and a second high-voltage power supply potentialVDD2. Further, if the first output signal Gout of the sixth signal line156 can have a fall time sufficiently shortened by the eleventh thinfilm transistor 121, the fifth thin film transistor 115 does not need toshorten the fall time of the first output signal Gout of the sixthsignal line 156. Therefore, in FIG. 6B, it is possible to set the firsthigh-voltage power supply potential VDD1 supplied by the power supplyline 171 lower than the second high-voltage power supply potential VDD2supplied by the power supply line 172. As a result, it is possible toease a shift in the threshold voltage of the third thin film transistor113, the fourth thin film transistor 114, and the fifth thin filmtransistor 115.

Next, a structure of a thin film transistor included in the pulse outputcircuit is described. An n-channel thin film transistor has higherfield-effect mobility than a p-channel thin film transistor. Therefore,in this embodiment, a structure of an n-channel thin film transistor isdescribed.

(Structure 1)

FIG. 17 shows a cross-sectional view of an embodiment of the thin filmtransistor. The thin film transistor shown in FIG. 17 has, over asubstrate 1101, a gate electrode 1103, a microcrystalline semiconductorlayer 1115 a, a mixed layer 1115 b, a layer 1129 c including anamorphous semiconductor, a gate insulating layer 1105 provided betweenthe gate electrode 1103 and the microcrystalline semiconductor layer1115 a, impurity semiconductor layers 1127 serving as a source regionand a drain region which are in contact with the layer 1129 c includingan amorphous semiconductor, and wirings 1125 which are in contact withthe impurity semiconductor layer 1127.

As the substrate 1101, a glass substrate, a ceramic substrate, a plasticsubstrate with heat resistance which can withstand process temperaturein manufacturing steps, or the like can be used. Alternatively, in thecase where the substrate does not need a light-transmitting property, asubstrate in which an insulating layer is provided on a surface of asubstrate of a metal such as a stainless steel alloy may be used. As aglass substrate, for example, an alkali-free glass substrate formedusing barium borosilicate glass, aluminoborosilicate glass,aluminosilicate glass, or the like may be used. Further, as thesubstrate 1101, the substrate may have any of the following sizes: thethird generation (e.g., 550 mm×650 mm), the 3.5th generation (e.g., 600mm×720 mm or 620 mm×750 mm), the fourth generation (e.g., 680 mm×880 mmor 730 mm×920 mm), the fifth generation (e.g., 1100 mm×1300 mm), thesixth generation (e.g., 1500 mm×1850 mm), the seventh generation (e.g.,1870 mm×2200 mm), the eighth generation (e.g., 2200 mm×2400 mm), theninth generation (e.g., 2400 mm×2800 mm), the tenth generation (e.g.,2850 mm×3050 mm), and the like.

The gate electrode 1103 can be a single layer or a stacked layerincluding a metal material such as molybdenum, titanium, chromium,tantalum, tungsten, aluminum, copper, neodymium, or scandium; or analloy material containing any of these materials as a main component.Alternatively, an AgPdCu alloy or a semiconductor layer typified bypolycrystalline silicon doped with an impurity element such asphosphorus may be used.

For example, as a two-layer structure of the gate electrode 1103, thefollowing structures are preferable: a two-layer structure of analuminum layer and a molybdenum layer stacked thereover, a two-layerstructure of a copper layer and a molybdenum layer stacked thereover, atwo-layer structure of a copper layer and a titanium nitride layer or atantalum nitride layer stacked thereover, and a two-layer structure of atitanium nitride layer and a molybdenum layer. As a three-layerstructure of the gate electrode 1103, a stack of a tungsten layer or atungsten nitride layer, a layer of an alloy of aluminum and silicon oran alloy of aluminum and titanium, and a titanium nitride layer or atitanium layer is preferable. When a metal layer functioning as abarrier layer is stacked over a layer with low electric resistance,electric resistance can be lowered and diffusion of a metal element fromthe metal layer into the semiconductor layer can be prevented.

Note that in order to improve adhesion between the gate electrode 1103and the substrate 1101, a nitride layer of any of the metal materialsdescribed above may be provided between the gate electrode 1103 and thesubstrate 1101.

The gate insulating layer 1105 can be a single layer or a stacked layerof a silicon oxide layer, a silicon nitride layer, a silicon oxynitridelayer, or a silicon nitride oxide layer by CVD, sputtering, or the like.

Note that in this specification, silicon oxynitride refers to a materialwhich contains more oxygen than nitrogen, and in the case wheremeasurement is performed using Rutherford backscattering spectrometry(RBS) and hydrogen forward scattering (HFS), silicon oxynitride includesoxygen, nitrogen, silicon, and hydrogen as composition ranging from 50to 70 atomic %, 0.5 to 15 atomic %, 25 to 35 atomic %, and 0.1 to 10atomic %, respectively. Further, silicon nitride oxide refers to amaterial which contains more nitrogen than oxygen, and in the case wheremeasurement is performed using RBS and HFS, silicon nitride oxidepreferably includes oxygen, nitrogen, silicon, and hydrogen ascomposition ranging from 5 to 30 atomic %, 20 to 55 atomic %, 25 to 35atomic %, and 10 to 30 atomic %, respectively. Note that percentages ofnitrogen, oxygen, silicon, and hydrogen fall within the ranges givenabove if the total number of atoms contained in silicon oxynitride orsilicon nitride oxide is defined as 100 atomic %.

A microcrystalline semiconductor included in the microcrystallinesemiconductor layer 1115 a is a semiconductor having an intermediatestructure between amorphous and crystalline structures (including singlecrystal and polycrystal). A microcrystalline semiconductor is asemiconductor having a third state that is stable in terms of freeenergy and is a crystalline semiconductor having short-range order andlattice distortion, in which columnar or needle-like crystals having agrain size of from 2 to 200 nm, preferably 10 to 80 nm, more preferably20 to 50 nm have grown in a direction normal to the substrate surface.Therefore, a crystal grain boundary is formed at the interface of thecolumnar or needle-like crystals in some cases.

The Raman spectrum of microcrystalline silicon, which is a typicalexample of a microcrystalline semiconductor, shifts to a lowerwavenumber side than 520 cm⁻¹ which represents single crystal silicon.That is, the peak of the Raman spectrum of microcrystalline silicon isbetween 520 cm⁻¹ which represents single crystal silicon and 480 cm⁻¹which represents amorphous silicon. Further, microcrystalline siliconcontains hydrogen or halogen at a concentration of at least 1 atomic %to terminate a dangling bond. Moreover, microcrystalline siliconcontains a rare gas element such as helium, argon, krypton, or neon tofurther promote lattice distortion, so that stability is increased and afavorable microcrystalline semiconductor can be obtained. Such amicrocrystalline semiconductor is disclosed in, for example, U.S. Pat.No. 4,409,134.

Further, it is preferable that the concentration of oxygen and nitrogencontained in the microcrystalline semiconductor layer 1115 a measured bysecondary ion mass spectrometry be less than 1×10¹⁸ atoms/cm³ becausethe crystallinity of the microcrystalline semiconductor layer 1115 a canbe improved.

Further, a semiconductor layer, which has lower energy at an urbach edgemeasured by constant photocurrent method (CPM) or photoluminescencespectroscopy and a smaller amount of absorption spectra of defects thana conventional amorphous semiconductor layer, is referred to as thelayer 1129 c including an amorphous semiconductor.

Note that amorphous silicon is a typical example of an amorphoussemiconductor in the layer 1129 c including an amorphous semiconductor.

In addition, the layer 1129 c including an amorphous semiconductor mayinclude nitrogen or an NH group.

FIGS. 18A and 18B each show an enlarged view of a region between thegate insulating layer 1105 and the impurity semiconductor layer 1127functioning as a source or drain region in FIG. 17. Particularly, themixed layer 1115 b will be described in detail.

As shown in FIG. 18A, the mixed layer 1115 b is provided between themicrocrystalline semiconductor layer 1115 a and the layer 1129 cincluding an amorphous semiconductor. In addition, the mixed layer 1115b includes microcrystalline semiconductor regions 1108 a and amorphoussemiconductor region 1108 b filling the space except themicrocrystalline semiconductor regions 1108 a. Specifically, the mixedlayer 1115 b includes the microcrystalline semiconductor regions 1108 awhich protrudes from the microcrystalline semiconductor layer 1115 a andthe amorphous semiconductor region 1108 b which is formed using asimilar kind of semiconductor as the layer 1129 c including an amorphoussemiconductor. Note that the amorphous semiconductor region 1108 bincluded in the mixed layer 1115 b may include semiconductor crystalgrains having a grain size from 1 nm to 10 nm, preferably, from 1 nm to5 nm.

The microcrystalline semiconductor regions 1108 a are formed using amicrocrystalline semiconductor and each have a conical or pyramidalshape or a projecting shape with a tip that narrows from the gateinsulating layer 1105 to the layer 1129 c including an amorphoussemiconductor. Note that the microcrystalline semiconductor regions 1108a may each have a conical or pyramidal shape or a projecting shape witha tip that widens from the gate insulating layer 1105 to the layer 1129c including an amorphous semiconductor.

As for the mixed layer 1115 b, in the case where each of themicrocrystalline semiconductor regions 1108 a have a projecting shapewith a tip that narrows from the gate insulating layer 1105 to the layer1129 c including an amorphous semiconductor, the mixed layer 1115 b onthe microcrystalline semiconductor layer 1115 a side accounts for alarger microcrystalline semiconductor region than the mixed layer 1115 bon the layer 1129 c including an amorphous semiconductor side. Thereason thereof is as follows: although the microcrystallinesemiconductor regions 1108 a grow in a thickness direction on a surfaceof the microcrystalline semiconductor layer 1115 a, when a gas whosesource gas contains nitrogen is added, or when a flow ratio of hydrogento silane is reduced to less than that in the deposition condition ofthe microcrystalline semiconductor layer and a gas whose source gascontains nitrogen is added as well, crystal growth of the semiconductorcrystal grains in the microcrystalline semiconductor regions 1108 a isrestrained, and the semiconductor crystal grains come to have a conicalor pyramidal shape, and an amorphous semiconductor are eventuallydeposited.

Note that the microcrystalline semiconductor regions 1108 a included inthe mixed layer 1115 b are semiconductors the quality of which isapproximately the same as the quality of the microcrystallinesemiconductor layer 1115 a, while the amorphous semiconductor region1108 b included in the mixed layer 1115 b is a semiconductor the qualityof which is approximately the same as the quality of the layer 1129 cincluding an amorphous semiconductor. Therefore, the interface betweenthe microcrystalline semiconductor layer and the layer containing anamorphous semiconductor is the interface between the microcrystallinesemiconductor regions 1108 a and the amorphous semiconductor region 1108b in the mixed layer; thus, in other words, the interface between themicrocrystalline semiconductor layer and the layer containing anamorphous semiconductor is uneven.

Since the mixed layer 1115 b includes the microcrystalline semiconductorregions 1108 a having a conical or pyramidal shape, resistance in thevertical direction (the thickness direction), that is, resistancebetween the microcrystalline semiconductor layer 1115 a and the impuritysemiconductor layer 1127 serving as a source or drain region can bereduced.

Accordingly, by forming the microcrystalline semiconductor layer 1115 aserving as a channel region, and providing, between the channel regionand the impurity semiconductor layers 1127 serving as a source regionand a drain region, the mixed layer 1115 b including themicrocrystalline semiconductor regions 1108 a having a conical orpyramidal shape, and the layer 1129 c including an amorphoussemiconductor formed using a well-ordered semiconductor layer which hasfewer defects and whose tail slope of a level at a band edge in thevalence band is steep, it is possible to reduce off-state-current of thethin film transistor and increase on-state-current and field-effectmobility.

In addition, as shown in FIG. 18B, a structure is possible where themixed layer 1115 b is provided between the microcrystallinesemiconductor layer 1115 a and the impurity semiconductor layer 1127,and the layer 1129 c including an amorphous semiconductor is not formedbetween the mixed layer 1115 b and the impurity semiconductor layer1127. In such a structure, it is preferable that the microcrystallinesemiconductor regions 1108 a account for smaller region than theamorphous semiconductor region 1108 b. In this manner, off-state-currentof the thin film transistor can be reduced. Further, it is possible toreduce resistance in the vertical direction (the thickness direction) inthe mixed layer 1115 b and resistance between a source region and adrain region, and to increase on-state-current of the thin filmtransistor.

In addition, the mixed layer 1115 b preferably includes nitrogen, for atypical example, an NH group or an NH₂ group. This is because defectsare reduced when nitrogen, for a typical example, an NH group or an NH₂group is bonded with dangling bonds of silicon atoms at the interfacebetween semiconductor crystal grains included in the microcrystallinesemiconductor regions 1108 a and at the interface between themicrocrystalline semiconductor regions 1108 a and the amorphoussemiconductor region 1108 b. Accordingly, by setting the concentrationof nitrogen at 1×10²⁰ cm⁻³ to 1×10²¹ cm⁻³, the dangling bonds of siliconatoms can be easily cross-linked with nitrogen, preferably an NH group,so that carriers can flow easily. Alternatively, the dangling bonds ofthe semiconductor atoms at the aforementioned interfaces are terminatedwith the NH₂ group, so that the defect level disappears. As a result,resistance in the vertical direction (the film thickness direction) atthe time of the application of voltage between the source electrode anddrain electrode of the thin film transistor which is in an on state isreduced. That is, field-effect mobility and on current of the thin filmtransistor are increased.

In addition, at the interface between the microcrystalline semiconductorregions 1108 a and the microcrystalline semiconductor region 1108 b, andat the interface between the semiconductor crystal grains, the defectswhich interfere with the carrier transfer can be reduced by a reductionin oxygen concentration in the mixed layer 1115 b.

Note that, in this case, the microcrystalline semiconductor layer 1115 arefers to a region having approximately uniform thickness. Further, theinterface between the microcrystalline semiconductor layer 1115 a andthe mixed layer 1115 b refers to a region where the region closest tothe gate insulating layer 1105 is extended in a plain portion of theinterface between the microcrystalline semiconductor regions 1108 a andthe microcrystalline semiconductor region 1108 b.

The total thickness of the microcrystalline semiconductor layer 1115 aand the mixed layer 1115 b, that is, the distance from the interfacebetween the gate insulating layer 1105 and the microcrystallinesemiconductor layer 1115 a to each of the tips of the microcrystallinesemiconductor regions 1108 a is from 3 nm to 80 nm, preferably from 5 nmto 30 nm, whereby off-state-current of the TFT can be reduced.

The impurity semiconductor layer 1127 is formed using amorphous siliconto which phosphorus is added, microcrystalline silicon to whichphosphorus is added, or the like. Note that in the case where ap-channel thin film transistor is formed as the thin film transistor,the impurity semiconductor layer 1127 is made of microcrystallinesilicon to which boron is added, amorphous silicon to which boron isadded, or the like. Note that when ohmic contact is formed between themixed layer 1115 b and the wirings 1125 or between the layer 1129 cincluding an amorphous semiconductor and the wirings 1125, the impuritysemiconductor layer 1127 is not necessarily formed.

In addition, in the case where the impurity semiconductor layer 1127 isformed using microcrystalline silicon to which phosphorus is added ormicrocrystalline silicon to which boron is added, characteristics of theinterface can be improved by a formation of a microcrystallinesemiconductor layer, for a typical example, a microcrystalline siliconlayer between the mixed layer 1115 b and the impurity semiconductorlayer 1127 or between the layer 1129 c including an amorphoussemiconductor and the impurity semiconductor layer 1127. In such amanner, it is possible to reduce resistance at the interface between themixed layer 1115 b and the impurity semiconductor layer 1127 or betweenthe layer 1129 c including an amorphous semiconductor and the impuritysemiconductor layer 1127. As a result, it is possible to increase anamount of a current flowing through a source region, themicrocrystalline semiconductor layer 1115 a, the mixed layer 1115 b, andthe layer 1129 c including an amorphous semiconductor, and a drainregion, which are included in the thin film transistor; thus, anincrease in on-state-current and the field-effect mobility can berealized.

Wirings 1125 illustrated in FIG. 19 can be a single layer or a stackedlayer including aluminum, copper, titanium, neodymium, scandium,molybdenum, chromium, tantalum, tungsten, or the like. Alternatively, analuminum alloy to which an element for preventing generation of hillocksis added (e.g., an Al—Nd alloy which can be used for the gate electrode1103) may be used. A layer may have a stacked-layer structure in which alayer on a side which is in contact with the impurity semiconductorlayer 1127 is formed using titanium, tantalum, molybdenum, tungsten, ornitride of any of these elements and aluminum or an aluminum alloy isformed thereover. Further, a stacked layer structure may be used inwhich upper and lower surfaces of aluminum or an aluminum alloy may besandwiched between any of titanium, tantalum, molybdenum, tungsten, ornitride thereof.

With the thin film transistor shown in FIGS. 18A and 18 b, and FIG. 19,off-state-current can be reduced and on-state-current and thefield-effect mobility can be increased. Further, since the channelregion is formed using a microcrystalline semiconductor layer, fewerdeterioration and higher reliability in electric characteristics can berealized. Moreover, since on-state-current is high, a reduction in anarea of the channel region, that is, an area occupied by the thin filmtransistor is smaller, and integration level of the thin film transistoris thus higher than with a thin film transistor whose channel region isformed using an amorphous silicon.

(Structure 2)

FIG. 19 shows a cross-sectional view of an embodiment of the thin filmtransistor. The thin film transistor shown in FIG. 19 includes the gateelectrode 1103 over the substrate 1101, the gate insulating layer 1105which covers the gate electrode 1103, a microcrystalline semiconductorlayer 1131 which functions as a channel region and is in contact withthe gate insulating layer 1105, a pair of layers 1132 including anamorphous semiconductor over the microcrystalline semiconductor layer1131, and the impurity semiconductor layers 1127 which function as asource region and a drain region and are in contact with the pair oflayers 1132 containing an amorphous semiconductor. Further, the thinfilm transistor shown in FIG. 19 includes wirings 1125 which are incontact with the impurity semiconductor layers 1127 and function as asource electrode and a drain electrode. In addition, a first insulatinglayer 1135 a is formed over a surface of the microcrystallinesemiconductor layer 1131. Further, second insulating layers 1135 c areformed over surfaces of the pair of layers 1132 including an amorphoussemiconductor and surface of the impurity semiconductor layer 1127.Furthermore, third insulating layers 1135 e are formed over surfaces ofthe wirings 1125.

A first microcrystalline semiconductor layer 1131 a in contact with thegate insulating layer 1105, and a second microcrystalline semiconductorlayer 1131 b having a plurality of conical or pyramidal protrusions(projections) are formed in the first microcrystalline semiconductorlayer 1131.

The microcrystalline semiconductor layer 1131 is formed using amicrocrystalline semiconductor which is similar to the microcrystallinesemiconductor layer 1115 a described in Embodiment 1. The secondmicrocrystalline semiconductor layer 1131 b can be formed in a mannersimilar to the microcrystalline semiconductor regions 1108 a included inthe mixed layer 1115 b described in Embodiment 1.

In a manner similar to the layer 1129 c including an amorphoussemiconductor described in Embodiment 1, the pair of layers 1132including an amorphous semiconductor can be formed using a well-orderedsemiconductor which has fewer defects and whose tail slope of a level ata band edge in the valence band is steeper than a conventional amorphoussemiconductor layer.

The first insulating layer 1135 a is formed using an oxide layer formedby oxidizing the microcrystalline semiconductor layer 1131, a nitridelayer formed by nitriding the microcrystalline semiconductor layer 1131,an oxynitride layer or a nitride oxide layer formed by nitriding andoxidizing the microcrystalline semiconductor layer 1131, or the like. Asa typical example of the first insulating layer 1135 a, a silicon oxidelayer, a silicon nitride layer, a silicon oxynitride layer, a siliconnitride oxide layer, or the like can be used.

The second insulating layers 1135 c are formed using oxide layers formedby oxidizing the pair of layers 1132 including an amorphoussemiconductor and the impurity semiconductor layers 1127, nitride layersformed by nitriding the pair of layers 1132 including an amorphoussemiconductor and the impurity semiconductor layers 1127, oxynitridelayers or nitride oxide layers formed by nitriding and oxidizing thepair of layers 1132 including an amorphous semiconductor and theimpurity semiconductor layers 1127, the impurity semiconductor layers1127, or the like. As a typical example of the second insulating layers1135 c, silicon oxide layers, silicon nitride layers, silicon oxynitridelayers, silicon nitride oxide layers, or the like can be used.

The third insulating layers 1135 e are formed using oxide layers formedby oxidizing the wirings 1125, nitride layers formed by nitriding thewirings 1125, oxynitride layers or nitride oxide layers formed bynitriding and oxidizing the wirings 1125, or the like. Note thatalthough the third insulating layers 1135 e are formed on top surfacesand side surfaces of the wirings 1125 in this case, the third insulatinglayers 1135 e may be formed only on side surfaces of the wirings 1125and are not necessarily be formed on top surfaces of the wirings 1125.As a typical example of the third insulating layers 1135 e, metal oxidelayers, metal nitride layers, metal oxynitride layers, metal nitrideoxide layers, or the like can be used. In this case, the metal refers toany of the metal elements in the description of the wirings 1125.

The pair of layers 1132 includes an amorphous semiconductor and thus hasa weak n-type conductivity. In addition, the pair of layers 1132including an amorphous semiconductor has lower density than themicrocrystalline semiconductor layer 1131. Therefore, the secondinsulating layers 1135 c formed by oxidizing or nitriding the amorphoussemiconductor layer are nondense insulating layers having low densityand a low insulating property. However, in the thin film transistordescribed in this embodiment, the first insulating layer 1135 a formedby oxidizing the microcrystalline semiconductor layer 1131 is formed ona back channel side. The microcrystalline semiconductor layer has higherdensity than the amorphous semiconductor layer, and the first insulatinglayer 1135 a thus has also high density and a high insulating property.Further, the second insulating layer 1131 b has a plurality of conicalor pyramidal protrusions (projections) and thus has an uneven surface.Therefore, a leak path between a source region and a drain region has along distance. Accordingly, a reduction in off-state-current of the thinfilm transistor can be realized.

In the thin film transistor described in this embodiment, amicrocrystalline semiconductor layer having a plurality of conical orpyramidal protrusions is used for a channel region, and a pair of layerscontaining an amorphous semiconductor are formed in contact with themicrocrystalline semiconductor layer; therefore, a larger amount ofon-state-current can be obtained than in a thin film transistor in whichan amorphous semiconductor is used for a channel region, and a smalleramount of off-state-current can be obtained than in a thin filmtransistor in which a microcrystalline semiconductor is used for achannel region.

By the use of a thin film transistor, as shown in Structure 1 andStructure 2 described above, in which a microcrystalline semiconductoris used for a channel region as the thin film transistor included in thepulse output circuit, degradation of characteristics of the thin filmtransistor can be suppressed, and deterioration in the display qualitycan be restrained. Further, in the case where a microcrystallinesemiconductor is used for a semiconductor layer of the thin filmtransistor, productivity can be improved, and an increase in the size ofthe display device, a reduction in cost, an improvement in yield, or thelike can thus be achieved

Note that the contents described in each drawing in this embodiment canbe freely combined with or replaced with the contents described in anyof the other embodiments as appropriate.

Embodiment 2

In this embodiment, an embodiment of a driver circuit having a structurewhich is different from the structure in the above embodiment isdescribed.

Driver circuits which function as shift registers are described withreference to FIGS. 7A to 7C, FIGS. 8A and 8B, FIGS. 9A and 9B, FIGS. 10Aand 10B, and FIG. 30. A shift register 700 includes first to J-th pulseoutput circuits 701_1 to 701_J (J is preferably a multiple of 4, whichis 4 or more) (see FIG. 7A). Unlike the embodiment above, a first clocksignal CK1 from a first wiring 702, a second clock signal CK2 from asecond wiring 703, a third clock signal CK3 from a third wiring 704, afourth clock signal CK4 from a fourth wiring 705, and a reset signal RESfrom a fifth wiring 706 are input to each of the stages of the first toJ-th pulse output circuits 701_1 to 701_J of the shift register 700shown in FIG. 7A. Further, a start pulse SP or a signal from a pulseoutput circuit in the previous stage (referred to as the previous stagesignal Lin) is input to each of the plurality of pulse output circuits.Furthermore, a signal from a pulse output circuit in the next stage(referred to as the next stage signal Rin) is input to each of theplurality of pulse output circuits. Moreover, the pulse output circuitin each stage outputs a first output signal Gout which is output to agate line, a data line, etc. and outputs a second output signal SRoutwhich is output to the pulse output circuit in the previous and/or thepulse output circuit in the next stage. Note that a dummy stage of thepulse output circuit, which outputs a signal which does not contributeto display in a display portion, may be provided. For example, in astructure where the pulse output circuit is used as a shift register ina gate driver and outputs pulses sequentially to n gate lines, J stages(n≤J) may be satisfied.

Note that the first clock signal CK1 to the fourth clock signal CK4sequentially deviate (are sequentially delayed) by a fourth of a cycle.Specifically, a (J−2)th clock signal CK2 is advanced from a (J−3)thclock signal CK1 by a fourth of a cycle, a (J−1)th clock signal CK3 isadvanced from the (J−2)th clock signal CK2 by a fourth of a cycle, aJ-th clock signal CK4 is advanced from the (J−1)th clock signal CK3 by afourth of a cycle, the J-th clock signal CK4 is advanced from the(J−3)th clock signal by a fourth of a cycle. As shown in FIG. 7B, as forthe pulse output circuit 701_1 in a first stage, which is an example ofa (J−3)th stage, a clock signal CK_N (in this case, N is 1) is input toa first terminal; the reset signal RES is input to a second terminal;any of the first to fourth clock signals (in this case, CK2) which isdifferent from the clock signal input to the first terminal is input toa third terminal; the previous stage signal Lin is input to a fourthterminal; the next stage signal Rin is input to a fifth terminal; thefirst output signal Gout is output from a sixth terminal; and the secondoutput signal SRout is output from a seventh terminal. As for the pulseoutput circuit 701_2 in a second stage, which is an example of a (J−2)thstage, a clock signal CK_N (in this case, N is 2) is input to a firstterminal; the reset signal RES is input to a second terminal; any of thefirst to fourth clock signals (in this case, CK3) which is differentfrom the clock signal input to the first terminal is input to a thirdterminal; the previous stage signal Lin is input to a fourth terminal;the next stage signal Rin is input to a fifth terminal; the first outputsignal Gout is output from a sixth terminal; and the second outputsignal SRout is output from a seventh terminal. As for the pulse outputcircuit 701_3 in a third stage, which is an example of a (J−1)th stage,a clock signal CK_N (in this case, N is 3) is input to a first terminal;the reset signal RES is input to a second terminal; any of the first tofourth clock signals (in this case, CK3) which is different from theclock signal input to the first terminal; the previous stage signal Linis input to a fourth terminal; the next stage signal Rin is input to afifth terminal; the first output signal Gout is output from a sixthterminal; and the second output signal SRout is output from a seventhterminal. As for the pulse output circuit 701_4 in a fourth stage, whichis an example of the J-th stage, a clock signal CK_N (in this case, N is4) is input to a first terminal; the reset signal RES is input to asecond terminal; any of the first to fourth clock signals (in this case,CK4) which is different from the clock signal input to the firstterminal is input to a third terminal; the previous stage signal Lin isinput to a fourth terminal; the next stage signal Rin is input to afifth terminal; the first output signal Gout is output from a sixthterminal; and the second output signal SRout is output from a seventhterminal. Note that the first clock signal CK1 to the fourth clocksignal CK4 become H-level signals (high power supply potential level)and L-level signals (low power supply potential level) repeatedly at aregular interval.

Next, an example of a specific circuit structure of the pulse outputcircuit is described with reference to FIG. 7C. Note that an example ofthe structure of the pulse output signal in the (J−3)th stage isdescribed below with reference to FIG. 7C. Note that the plurality ofpulse output circuits differ from each other in that the terminals towhich any of the first to fourth clock signals CK1 to CK4 is input arechanged, as described above. As shown in FIG. 7C, the circuit structureof the pulse output circuit is similar to that of the pulse out putcircuit described in Embodiment 1 with reference to FIG. 1D, and theexplanation given above is thus incorporated herein.

Next, operation of the shift register shown in FIGS. 7A to 7C isdescribed with reference to FIGS. 8A and 8B, FIGS. 9A and 9B, FIGS. 10Aand 10B, FIGS. 11A and 11B. Note that for explanation, as shown in FIG.8A, a connection node of the second terminal of the second thin filmtransistor 112, the gate of the sixth thin film transistor 116, and thegate of the seventh thin film transistor 117 is denoted by a node A in amanner similar to that in Embodiment 1. Further, in order tospecifically describe the operation of the shift register, a firstperiod T1, a second period T2, a third period T3, a fourth period T4,and a fifth period T5, which are shown in a timing chart in FIG. 8B, areseparately used for explanation. Note that in the following description,the first to eleventh thin film transistors 111 to 121 are N-channelthin film transistors and are in a conduction state when voltage (Vgs)between the gate and the source exceeds a threshold voltage (Vth). Notethat in FIG. 5B, the first to eleventh thin film transistors 111 to 121used for a shift register included in a gate driver, and a period 201 isa vertical retrace period and a period 202 is a gate selection period.Further, in the timing chart in FIG. 8B shows specific examples of thewaveforms of the first clock signal CK1, the second clock signal CK2,the third clock signal CK3, the fourth clock signal CK4, the resetsignal RES, the previous stage signal Lin, the next stage signal Rin,and the second output signal SRout of each stage (e.g., SRout1 of thefirst stage). Furthermore, the high power supply potential level and thelow power supply potential level of each signal are VDD and VSS,respectively. In addition, a first output signal Gout1 is omitted herebecause it has a waveform which is the same as that of the second outputsignal SRout1.

A difference between the structure described in this embodiment and thestructure described in Embodiment 1 is the cycle of charge and dischargethat each of the clock signals (the first to fourth clock signals CK1 toCK4) repeats. In this embodiment, the number of charges and dischargesof each clock signal can be made approximately half of that of a clocksignal CK and the inverted clock signal CKB in Embodiment 1. Therefore,a reduction in frequency of a clock signal can be achieved, and areduction in power consumption can be realized. In particular, in adriver circuit of a large display device, parasitic capacitance, gatecapacitance, or the like of each wiring is increased. By a reduction inthe number of charges and discharges of a clock signal used for a shiftregister to be driven, it is possible to shorten a time for the rising(a shift from VSS to VDD) or the falling (a shift from VDD to VSS) of asignal used for storing electricity in each wiring. Therefore, a drivercircuit of a display device which is capable of high quality displayscan be obtained.

In the first period T1, the reset signal RES becomes an H-level signaland the first thin film transistor 111 whose gate is connected to thesecond signal line 152 is conducting. At the time, the second clocksignal CK2, the first clock signal CK1, the previous stage signal Lin,and the next stage signal Rin are L-level signals. As shown in FIG. 9A,after the first thin film transistor 111 is conducting, the second thinfilm transistor 112, the third thin film transistor 113, the fourth thinfilm transistor 114, and the fifth thin film transistor 115 areconducting. Therefore, a current flows as shown by a dotted arrow inFIG. 9A, and the potential of each wiring in the first period T1 isdetermined as shown in FIG. 8B. That is, the first period T1 is a periodduring which the potential of each wiring in the pulse output circuit isreset (to VSS). In addition, in the first period T1, an L-level signalis output as the second output signal SRout.

When the reset signal RES is input to the gate of the first thin filmtransistor 111 every vertical retrace period which is the period 201,the potential of each of the thin film transistors can be set at VSS.Therefore, a so-called dynamic circuit, which is described in thisembodiment and which is driven with the use of a node in a floatingstate, can initialize each node, whereby noise immunity and operationreliability can be improved to be equal to those of a static circuit.

Next, in the second period T2, the previous stage signal Lin is anH-level signal, and the eighth thin film transistor 118 and the tenththin film transistor 120 whose gates are each connected to the fourthsignal line 154 are thus conducting. At the time, the first clock signalCK1, the second clock signal CK2, the reset signal RES, and the nextstage signal Rin are L-level signals. Further, at the time, the eighththin film transistor 118 is conducting, as illustrated in FIG. 9B. Thesecond thin film transistor 112 is conducting as in the first period T1,and a current flows, as shown by a dotted arrow in FIG. 9B. At the time,the node A uses the second terminal of the eighth thin film transistor118 as the source; therefore, a potential of the node A becomes a valueVDD-Vth obtained by subtraction of the threshold voltage Vth of theeighth thin film transistor 118 from a value of a potential of the firstpower supply line 131. When the second terminal of the eighth thin filmtransistor 118 is VDD-Vth, the thin film transistor 118 arenon-conducting and the node A enters into a floating state whilemaintaining VDD-Vth. Note that as shown in FIG. 9B, since the sixth thinfilm transistor 116 and the seventh thin film transistor 117 areconducting, and since the first signal line 151 is VSS, the potential ofeach wiring in the second period T2 is determined as in FIG. 9B. Thatis, the second period T2 is a period during which the node A in thepulse output circuit is brought into a floating state. In addition, inthe second period T2, an L-level signal is output as the second outputsignal SRout1.

Next, in the third period T3, the first clock signal CK1 becomes anH-level signal. At the time, the second clock signal CK2, the resetsignal RES, the previous stage signal Lin, and the next stage signal Rinare L-level signals. Further, at the time, as shown in FIG. 10A, thesixth thin film transistor 116 and the seventh thin film transistor 117are conducting, that is, the sixth thin film transistor 116 and theseventh thin film transistor 117 are in a state where current flowsbetween a source and a drain (a dotted arrow in FIG. 10A), and apotential of each second terminal (the source side) of the sixth thinfilm transistor 116 and the seventh thin film transistor 117 starts toincrease. There is capacitive coupling due to parasitic capacitancebetween a gate and a source of each of the sixth thin film transistor116 and the seventh thin film transistor 117, so that a potential of agate of the node A in a floating state increases as a potential of thesecond terminal serving as the source increases (bootstrap operation). Apotential of the node A eventually becomes higher than VDD+Vth, and thesecond terminal of each of the sixth thin film transistor 116 and theseventh thin film transistor 117 thus has a potential of VDD. Therefore,an H-level signal is output as the second output signal SRout1 in thethird period T3, that is, a potential of the node A in a floating stateis raised by the bootstrap operation and the first output signal Gout1and the second output signal SRout1 are output as H-level signals. Then,the second output signal SRout1 is input as the previous stage signalLin in the pulse output circuit in the second stage.

Note that as shown in FIG. 8B, with the second thin film transistor 112whose gate is supplied with high-voltage power supply potential VDD,advantages described below are obtained.

Without the second thin film transistor 112 whose gate is supplied withhigh-voltage power supply potential VDD, if a potential of the node A israised by bootstrap operation, a potential of a source which is thesecond terminal of the eighth thin film transistor 118 increases to avalue higher than the high power supply potential VDD. Then, the firstterminal of the eighth thin film transistor 118 comes to serve as thesource thereof. Therefore, in the eighth thin film transistor 118, alarge amount of bias voltage is applied and thus great stress is appliedbetween a gate and a source and between the gate and a drain in thethird period T3, which can cause deterioration in the thin filmtransistor.

With the second thin film transistor 112 whose gate is supplied withhigh-voltage power supply potential VDD, the potential of the node A israised by bootstrap operation, but at the same time, an increase in thepotential of the second terminal of the eighth thin film transistor 118can be prevented. In other words, with the second thin film transistor112, the level of a negative bias voltage applied between a gate and asource of the eighth thin film transistor 118 can be lowered.Accordingly, with the circuit structure in this embodiment, the level ofa negative bias voltage applied between a gate and a source of the thinfilm transistor can be lowered, so that deterioration in the eighth thinfilm transistor 118, which is due to stress, can further be suppressed.

Note that the second thin film transistor 112 are provided so as to beconnected, through the first terminal and the second terminal of thesecond thin film transistor 112, between the second terminal of theeighth thin film transistor 118 and the gate of the sixth thin filmtransistor 116, or between the second terminal of the eighth thin filmtransistor 118 and the gate of the seventh thin film transistor 117.

Note that the second thin film transistor 112 may be connected to thethird power supply line 2801 to which conduction holding potential VCCshown in FIG. 28A is supplied in a manner similar to that ofEmbodiment 1. Alternatively, a twelfth thin film transistor 2802 shownin FIG. 28B may be provided

Next, in the fourth period T4, the next stage signal Rin (SRout2 in FIG.2B) obtained from the pulse output circuit in the second stage becomesan H-level signal, and the ninth thin film transistor 119 whose gate isconnected to the fifth signal line 155 is thus conducting. At the time,the second clock signal CK2 is an H-level signal, and the first clocksignal CK1, the reset signal RES, and the previous stage signal Lin areL-level signals. The third thin film transistor 113, the fourth thinfilm transistor 114, the fifth thin film transistor 115, and theeleventh thin film transistor 121 are conducting. The second thin filmtransistor 112 is conducting as in the third period T3, and each gate ofthe sixth thin film transistor 116 and the seventh thin film transistor117 is set at VSS; thus, the sixth thin film transistor 116 and theseventh thin film transistor 117 are non-conducting. Therefore, acurrent flows as shown by a dotted arrow in FIG. 10B, and the potentialof each wiring in the fourth period T4 is thus determined as in FIG. 8B.That is, in the fourth period T4, the first output signal Gout1 and thesecond output signal SRout1 are L-level signals.

Note that in the fourth period T4, a signal used for the eleventh thinfilm transistor 121 to be conducting (in this case, the second clocksignal CK2) is supplied, so that a potential of the sixth signal line156 which outputs Gout falls rapidly. Therefore, a driver circuit withfewer malfunction can be obtained. Further, since the load on the thirdthin film transistor 113, the fourth thin film transistor 114, and thefifth thin film transistor 115 can be reduced, it is possible to reducedeterioration in the thin film transistors. Note that as shown in FIG.30, the eleventh thin film transistor 121 is formed using a plurality ofeleventh thin film transistors 121_1 to 121_3, and clock signalsdifferent from clock signals supplied to the first signal line 151 (inthis case, the second clock signal CK2, the third clock signal CK3, andthe fourth clock signal CK4) are supplied from third signal lines 153_1to 153_3 to the eleventh thin film transistors 121_1 to 121_3. Further,the eleventh thin film transistors 121_1 to 121_3 are controlled to beconducting or not to be conducting and the load on the third thin filmtransistor 113, the fourth thin film transistor 114, and the fifth thinfilm transistor 115 is reduced. Therefore, it is possible to reducedeterioration in the thin film transistors.

Then, the fifth period T5 is described as a period T5-1 and a periodT5-2, in which the H-level signals or the L-level signals of the firstclock signal CK1 and the third clock signal CK3 are input incombination. First, the period T5-1 is described. In the period T5-1,the first clock signal CK1 is an H-level signal or an L-level signal,and the third clock signal CK3, the reset signal RES, the previous stagesignal Lin, and the next stage signal Rin are L-level signals. The firstthin film transistor 111, the eighth thin film transistor 118, the ninththin film transistor 119, and the tenth thin film transistor 120 arenon-conducting, and the third thin film transistor 113, the fourth thinfilm transistor 114, and the fifth thin film transistor 115 enter into afloating state while maintaining the same gate potentials as in thefourth period. That is, the third thin film transistor 113, the fourththin film transistor 114, and the fifth thin film transistor 115 arekept in a conduction state. Further, the second thin film transistor 112is conducting as in the fourth period T4, and the gate potential of eachof the sixth thin film transistor 116 and the seventh thin filmtransistor 117 is set at VSS; thus, the sixth thin film transistor 116and the seventh thin film transistor 117 is non-conducting. Furthermore,the eleventh thin film transistor 121 is non-conducting. Therefore, acurrent flows as shown by a dotted arrow in FIG. 11A, and the potentialof each wiring in the period T5-1 is determined as shown in FIG. 11A.Next, in the period T5-2, the first clock signal CK1 is an H-levelsignal or an L-level signal, the third clock signal CK3 is an H-levelsignal, and the reset signal RES, the previous stage signal Lin, and thenext stage signal Rin are L-level signals. As in the period T5-1, thefirst thin film transistor 111, the eighth thin film transistor 118, theninth thin film transistor 119, and the tenth thin film transistor 120are non-conducting; thus, the third thin film transistor 113, the fourththin film transistor 114, and the fifth thin film transistor 115 enterinto a floating state while maintaining the same gate potentials as inthe fourth period. That is, the third thin film transistor 113, thefourth thin film transistor 114, and the fifth thin film transistor 115are kept in a conduction state. Further, the second thin film transistor112 is conducting as in the fourth period T4, and gate potential of eachof the sixth thin film transistor 116 and the seventh thin filmtransistor 117 is set at VSS; thus, the sixth thin film transistor 116and the seventh thin film transistor 117 is non-conducting. Furthermore,the eleventh thin film transistor 121 is conducting. Therefore, acurrent flows as shown by a dotted arrow in FIG. 11B, and the potentialof each wiring in the period T5-2 is determined as shown in FIG. 8B.That is, in the fifth period T5, L-level signals are output as the firstoutput signal Gout1 and the second output signal SRout1.

Note that a structure can be used where the capacitor 2901 is added, ina manner similar to that of the structure shown in Embodiment 1 withreference to FIG. 29.

Note that as described in Structure 1 and Structure 2 in Embodiment 1,by the use of a thin film transistor in which a microcrystallinesemiconductor is used for a channel region as the thin film transistorincluded in the pulse output circuit described in this embodiment,degradation in characteristics of the thin film transistor can besuppressed, and deterioration in the display quality can be restrained.Further, in the case where a microcrystalline semiconductor is used fora semiconductor layer of the thin film transistor, productivity can beimproved. Thus, an increase in the size of the display device, areduction in cost, an improvement in yield, or the like can be achieved

Note that the contents described in each drawing in this embodiment canbe freely combined with or replaced with the contents described in anyof the other embodiments as appropriate.

Embodiment 3

In this embodiment, examples of a display element, a display devicewhich is a device having a display element; a light-emitting element,and a light-emitting device which is a device having a light-emittingelement are described. Note that a display element, a display devicewhich is a device having a display element, a light-emitting element,and a light-emitting device which is a device having a light-emittingelement can employ a variety of types and can include a variety ofelements. For example, a display medium whose contrast, luminance,reflectivity, transmittance, or the like is changed by electromagneticaction, such as an EL (electroluminescent) element (e.g., an EL elementincluding organic and inorganic materials, an organic EL element, or aninorganic EL element), an LED (e.g., a white LED, a red LED, a greenLED, or a blue LED), a transistor which emits light depending on theamount of current), an electron emitter, a liquid crystal element,electronic ink, an electrophoretic element, a grating light valve (GLV),a plasma display panel (PDP), a digital micromirror device (DMD), apiezoelectric ceramic display, or a carbon nanotube can be used as adisplay element, a display device, a light-emitting element, and alight-emitting device. Note that display devices having EL elementsinclude an EL display; display devices having electron emitters includea field emission display (FED), an SED-type flat panel display (SED:surface-conduction electron-emitter display), and the like; displaydevices having liquid crystal elements include a liquid crystal display(e.g., a transmissive liquid crystal display, a transflective liquidcrystal display, a reflective liquid crystal display, a direct-viewliquid crystal display, or a projection liquid crystal display); anddisplay devices having electronic ink include electronic paper.

First, an example of d system block of a liquid crystal display deviceis described with reference to FIG. 12A. The liquid crystal displaydevice includes a circuit 5361, a source driver 5362, a gate driver5363_1, a gate driver 5363_2, a pixel portion 5364, a circuit 5365, anda lighting device 5366. A plurality of wirings 5371 which are extendedfrom the source driver 5362 and a plurality of wirings 5372 which areextended from the gate drivers 5363_1 and 5363_2 are provided in thepixel portion 5364. Moreover, pixels 5367 which include display elementssuch as liquid crystal elements are provided in a matrix in respectiveregions where the plurality of wirings 5371 and the plurality of wirings5372 is provided in matrix.

The circuit 5361 has a function of supplying a signal, voltage, current,or the like to the source driver 5362, the gate driver 5363_1, the gatedriver 5363_2, and the circuit 5365 in response to a video signal 5360and functions as a controller, a control circuit, a timing generator, apower supply circuit, a regulator, or the like. In this embodiment, forexample, the circuit 5361 supplies a signal line driver circuit startsignal (SSP), a signal line driver circuit clock signal (SCK), a signalline driver circuit inverted clock signal (SCKB), video signal data(DATA), or a latch signal (LAT) to the source driver 5362.Alternatively, as an example, the circuit 5361 supplies a scan linedriver circuit start signal (GSP), a scan line driver circuit clocksignal (GCK), or a scan line driver circuit inverted clock signal (GCKB)to the gate driver 5363_1 and the gate driver 5363_2. Furtheralternatively, the circuit 5361 supplies a backlight control signal(BLC) to the circuit 5365. Note that this embodiment is not limitedthereto, and the circuit 5361 can supply various other signals,voltages, currents, or the like to the source driver 5362, the gatedriver 5363_1, the gate driver 5363_2, and the circuit 5365.

The source driver 5362 has a function of outputting video signals to theplurality of wirings 5371 in response to a signal supplied from thecircuit 5361 (e.g., SSP, SCK, SCKB, DATA, or LAT), and functions as asignal line driver circuit. The gate driver 5363_1 and the gate driver5363_2 each have a function of outputting scan signals to the pluralityof wirings 5372 in response to a signal supplied from the circuit 5361(e.g., GSP, GCK, or GCKB), and functions as a scan line driver circuit.The circuit 5365 has a function of controlling the luminance (or theaverage luminance) of the lighting device 5366 by controlling the amountof electric power supplied to the lighting device 5366, time to supplythe electric power to the lighting device 5366, or the like inaccordance with the signal (BLC) supplied from the circuit 5361. Thecircuit 5365 can function as a power supply circuit.

Note that when video signals are input to the plurality of wirings 5371,the plurality of wirings 5371 can function as signal lines, video signallines, source lines, or the like. When scan signals are input to theplurality of wirings 5372, the plurality of wirings 5372 functions assignal lines, scan lines, gate lines, or the like.

Note that when the same signal is input to the gate driver 5363_1 andthe gate driver 5363_2 from the circuit 5361, scan signals output fromthe gate driver 5363_1 to the plurality of wirings 5372 and scan signalsoutput from the gate driver 5363_2 to the plurality of wirings 5372 haveapproximately the same timings in many cases. Accordingly, load causedby driving of the gate drivers 5363_1 and 5363_2 can be reduced. Thus,the display device can be made larger. Alternatively, the display devicecan have higher definition. Alternatively, since the channel width ofthin film transistors included in the gate drivers 5363_1 and 5363_2 canbe reduced, a display device with a narrower frame can be obtained. Notethat this embodiment is not limited thereto, and the circuit 5361 cansupply different signals to the gate driver 5363_1 and the gate driver5363_2.

Note that one of the gate driver 5363_1 and the gate driver 5363_2 canbe eliminated.

Note that a wiring such as a capacitor line, a power supply line, or ascan line can be additionally provided in the pixel portion 5364. Then,the circuit 5361 can output a signal, a voltage, or the like to such awiring. Further, a circuit similar to the gate driver 5363_1 or thegate, driver 5363_2 can be additionally provided. The additionallyprovided circuit can output a signal such as a scan signal to theadditionally provided wiring.

Note that the pixel 5367 can include a light-emitting element such as anEL element as a display element. In that case, as illustrated in FIG.12B, since the display element can emit light, the circuit 5365 and thelighting device 5366 can be eliminated. Moreover, in order to supplyelectric power to the display element, a plurality of wirings 5373 whichcan function as power supply lines can be provided in the pixel portion5364. The circuit 5361 can apply a power supply voltage called voltage(ANO) to the wirings 5373. The wirings 5373 can be separately connectedto the pixels in accordance with color elements or can be connected toall the pixels.

Note that FIG. 12B shows an example in which the circuit 5361 suppliesdifferent signals to the gate driver 5363_1 and the gate driver 5363_2.The circuit 5361 supplies a signal such as a scan line driver circuitstart signal (GSP1), a scan line driver circuit clock signal (GCK1), ora scan line driver circuit inverted clock signal (GCKB1) to the gatedriver 5363_1. In addition, the circuit 5361 supplies a signal such as ascan line driver circuit start signal (GSP2), a scan line driver circuitclock signal (GCK2), or a scan line driver circuit inverted clock signal(GCKB2) to the gate driver 5363_2. In that case, the gate driver 5363_1can scan only wirings in odd-numbered rows of the plurality of wirings5372 and the gate driver 5363_2 can scan only wirings in even-numberedrows of the plurality of wirings 5372. Accordingly, the drivingfrequency of the gate driver 5363_1 and the gate driver 5363_2 can belowered, whereby power consumption can be reduced. Alternatively, thearea in which a flip-flop of one stage can be laid out can be madelarger. Thus, a display device can have higher definition.Alternatively, the size of a display device can be increased. Note thatthis embodiment is not limited thereto, and the circuit 5361 can outputthe same signal to the gate driver 5363_1 and the gate driver 5363_2 asin FIG. 12A.

Note that as in FIG. 12B, the circuit 5361 can supply different signalsto the gate driver 5363_1 and the gate driver 5363_2 in FIG. 12A.

The above is the description of one example of the system block of thedisplay device.

Next, examples of structures of the display device will be describedwith reference to FIGS. 13A to 13D.

In FIG. 13A, circuits which have a function of outputting signals to thepixel portion 5364 (e.g., the source driver 5362, the gate driver5363_1, and the gate driver 5363_2) are formed over a substrate 5380where the pixel portion 5364 is also formed. In addition, the circuit5361 is formed over a substrate which is different from the substratewhere the pixel portion 5364 is formed. In this manner, since the numberof external components is reduced, a reduction in cost can be achieved.Alternatively, since the number of signals or voltages input to thesubstrate 5380 is reduced, the number of connections between thesubstrate 5380 and the external component can be reduced. Accordingly,an improvement in reliability or an increase in yield can be achieved.

Note that in the case where the circuit is formed over a substrate whichis different from the substrate where the pixel portion 5364 is formed,the substrate can be mounted on a flexible printed circuit (FPC) by tapeautomated bonding (TAB). Alternatively, the substrate can be mounted onthe same substrate 5380 as the pixel portion 5364 by chip on glass(COG).

In the case where the circuit is formed over a different substrate fromthe pixel portion 5364, a transistor formed using a single crystalsemiconductor can be formed on the substrate. Therefore, the circuitformed over the substrate can have advantages such as an improvement indriving frequency, an improvement in driving voltage, or a reduction invariation in output signals.

Note that a signal, voltage, current, or the like is input from anexternal circuit through an input terminal 5381 in many cases.

In FIG. 1313B, circuits with low driving frequency (e.g., the gatedriver 5363_1 and the gate driver 5363_2) are formed over the substrate5380 where the pixel portion 5364 is formed. In addition, the circuit5361 and the source driver 5362 are formed over a substrate which isdifferent from the substrate where the pixel portion 5364 is formed. Inthis manner, the circuit formed over the substrate 5380 can beconstituted by thin film transistors with lower field-effect mobility ascompared to that of a transistor formed using a single crystalsemiconductor (also referred to as a MOS transistor). Thus, amicrocrystalline semiconductor can be used for a channel region of thethin film transistor. Accordingly, an increase in the size of thedisplay device, a reduction in the number of steps, a reduction in cost,an improvement in yield, or the like can be achieved.

Note that as illustrated in FIG. 13C, part of the source driver 5362 (asource driver 5362 a) can be formed over the substrate 5380 where thepixel portion 5364 is formed, and the other part of the source driver5362 (a source driver 5362 b) can be formed over a substrate which isdifferent from the substrate where the pixel portion 5364 is formed. Thesource driver 5362 a often includes a circuit which can be formed usinga thin film transistor with low field-effect mobility (e.g., a shiftregister, a selector, or a switch). The source driver 5362 b oftenincludes a circuit which is preferably formed using a MOS transistorwith high field-effect mobility and few variations in characteristics(e.g., a shift register, a latch circuit, a buffer circuit, a DAconverter circuit, or an AD converter circuit). Accordingly, as in FIG.13B, a microcrystalline semiconductor can be used for a channel regionof the thin film transistor. Further, the number of external componentscan be reduced.

In FIG. 13D, part of the circuit 5361 (a circuit 5361 a) is formed overthe substrate 5380 over which the pixel portion 5364 is formed, and theother part of the circuit 5361 (a circuit 5361 b) is formed over asubstrate which is different from the substrate where the pixel portion5364 is formed. The circuit 5361 a often includes a circuit which can beformed using a thin film transistor with lower field-effect mobility ascompared to that of a MOS transistor (e.g., a switch, a selector, or alevel shift circuit). Moreover, the circuit 5361 b often includes acircuit which is preferably formed using a MOS transistor with highfield-effect mobility and few variations (e.g., a shift register, atiming generator, an oscillator, a regulator, or an analog buffer).

Note that also in FIGS. 13A to 13C, the circuit 5361 a can be formedover the same substrate as the pixel portion 5364, and the circuit 5361b can be formed over a substrate which is different from the substratewhere the pixel portion 5364 is formed.

Here, for the gate drivers 5363_1 and 5363_2, any of the shift registersin Embodiment 1 or 2 can be used. In that case, the gate drivers 5363_1and 5363_2 and the pixel portion are formed over the same substrate,whereby all the thin film transistors formed over the substrate can havethe same polarity. Accordingly, a reduction in the number of steps, animprovement in yield, an improvement in reliability, or a reduction incost can be realized. In particular, when all the thin film transistorsare n-channel transistors, microcrystalline semiconductors can be usedfor semiconductor layers of the thin film transistors. Thus, an increasein the size of the display device, a reduction in cost, an increase inyield, or the like can be realized. In addition, since themicrocrystalline semiconductor is used for the semiconductor layer,deterioration in characteristics of the thin film transistor can besuppressed, whereby the life of the display device can be made longer.

Note that the contents described in each drawing in this embodiment canbe freely combined with or replaced with the contents described in anyof the other embodiments as appropriate.

Embodiment 4

In this embodiment, an example of a source driver is described.

An example of a source driver is described with reference to FIG. 14A.The source driver includes a plurality of circuits 602_1 to 602_N (N isa natural number), a circuit 600, and a circuit 601. The circuits 602_1to 602_N each include a plurality of thin film transistors 603_1 to603_k (k is a natural number). The thin film transistors 603_1 to 603_khave the same conductivity type as the thin film transistors included inthe pulse output circuit in the shift register described in theembodiment above.

The relation of connection in the source driver is described taking thecircuit 602_1 as an example. Each first terminal of the thin filmtransistors 603_1 to 603_k is connected to a wiring 6051. Secondterminals of the thin film transistors 603_1 to 603_k are connected towirings S1 to Sk, respectively. Gates of the thin film transistors 603_1to 603_k are respectively connected to wirings 604_1 to 604_k. Forexample, the first terminal of the thin film transistor 603_1 isconnected to the wiring 605_1; a second terminal of the thin filmtransistor 603_1 is connected to the wiring S1; and the gate of the thinfilm transistor 603_1 is connected to the wiring 604_1.

The circuit 600 has a function of supplying signals to the circuits602_1 to 602_N through the wirings 604_1 to 604_k and can function as ashift register, a decoder, or the like. The signals are digital signalsin many cases and can function as a selection signals. The wirings 604_1to 604_k can function as signal lines. The circuit 601 has a function ofoutputting signals to the circuits 602_1 to 602_N and can function asvideo signal generation circuits or the like. For example, the circuit601 supplies the signal to the circuit 602_1 through the wiring 605_1and simultaneously supplies the signal to the circuit 602_2 through thewiring 605_2. The signals are digital signals in many cases and canfunction as a selection signals. The wirings 605_1 to 605_k can functionas signal lines.

The circuits 602_1 to 602_N each have a function of selecting a wiringto which an output signal of the circuit 601 is output and can thusfunction as selector circuits. For example, the circuit 602_1 has afunction of selecting from among the wirings S1 to Sk which wiring tooutput a signal which is intended to be output from the circuit 601 tothe wiring 605_1.

The transistors 603_1 to 603_N have a function of controlling aconduction state between the wiring 605_1 and each of the wirings S1 toSk in accordance with an output signal from the circuit 600 and functionas switches.

Next, operation of the source driver shown in FIG. 14A is described withreference to a timing chart in FIG. 14B. FIG. 14B shows examples of asignal 614_1 input to the wiring 604_1, a signal 614_2 input to thewiring 604_2, a signal 614_k input to the wiring 604_k, a signal 615_1input to the wiring 605_1, and a signal 615_2 input to the wiring 605_2.

Note that one operation period of the source driver corresponds to onegate selection period in a display device. One gate selection period isa period during which a pixel in a row is selected and a video signalcan be written to the pixel.

Note that one gate selection period is divided into a period T0 and aperiod T1 to a period Tk. The period T0 is a period during which aprecharge voltage is simultaneously applied to pixels in a selected row,and can be a precharge period. Each of the periods T1 to Tk is a periodduring which video signals are written to pixels in a selected row, andcan be a write period.

Note that for simplicity, operation of the source driver is describedtaking operation of the circuit 602_1 as an example.

First, in the period T0, the circuit 600 outputs H-level signals to thewirings 604_1 to 604_k. Accordingly, the thin film transistors 603_1 to603_k each have electrical continuity between the source and the drain,whereby the wiring 605_1 and the wirings S1 to Sk are conducting. At thetime, the circuit 601 applies a precharge voltage Vp to the wiring605_1, so that the precharge voltage Vp is output to the wirings S1 toSk through the thin film transistors 603_1 to 603_k, respectively. Then,the precharge voltage Vp is written to the pixels in a selected row, sothat the pixels in the selected row are precharged.

Next, in the period T1, the circuit 600 outputs an H-level signal to thewiring 604_1. Accordingly, the thin film transistor 603_1 has electricalcontinuity between the source and the drain, whereby the wiring 605_1and the wiring S1 are conducting. Moreover, the wiring 605_1 and thewirings S2 to Sk are non-conducting. At the time, if the circuit 601outputs a signal Data (S1) to the wiring 605_1, the signal Data (S1) isoutput to the wiring S1 through the thin film transistors 603_1. In thismanner, the signal Data (S1) is written to, among pixels connected tothe wiring S1, pixels in the selected row.

Next, in the period T2, the circuit 600 outputs an H-level signal to thewiring 604_2. Accordingly, the thin film transistor 603_2 has electricalcontinuity between the source and the drain, whereby the wiring 6052 andthe wiring S2 are conducting. Moreover, the wiring 605_1 and the wiringsS1 are non-conducting, and the wiring 605_1 and the wirings S3 to Skremain in a non-conduction state. At the time, if the circuit 601outputs a signal Data (S2) to the wiring 605_1, the signal Data (S2) isoutput to the wiring S2 through the thin film transistor 603_2. In thismanner, the signal Data (S2) is written to, among the pixels connectedto the wiring S2, the pixels in the selected row.

After that, the circuit 600 sequentially outputs H level signals to thewirings 604_1 to 604_k until the end of the period Tk, so that thecircuit 600 sequentially outputs the H level signals to the wirings604_3 to 604_k from the period T3 to the period Tk, as in the period T1and the period T2. Therefore, the transistors 603_3 to 603_ksequentially have electrical continuity between the source and thedrain; thus, the thin film transistors 603_1 to 603_k sequentially haveelectrical continuity between the source and the drain. Accordingly,signals output from the circuit 601 are sequentially output to thewirings S1 to Sk. In this manner, the signals can be sequentiallywritten to the pixels in the selected row.

The above is the description of an example of the source driver. Sincethe source driver in this embodiment includes the circuit functioning asa selector, the number of signals or the number of wirings can bereduced. Further, since a precharge voltage is written to a pixel beforea video signal is written to the pixel (in the period T0), a write timeof the video signal can be shortened. Accordingly, an increase in thesize of a display device and higher resolution of the display device canbe achieved. However, this embodiment is not limited to this, and theperiod T0 may be eliminated so that the pixel is not precharged.

Note that if k is too large, a write time for the pixel is shortened,whereby writing of a video signal to the pixel is not completed in thewrite time in some cases. Accordingly, k≤6 is preferable; k≤3 is morepreferable, and k=2 is much more preferable.

In specific, in the case where a color element of a pixel is dividedinto n (n is a natural number), it is possible td set k=n. For example,in the case where a color element of a pixel is divided into red (R),green (G), and blue (B), it is possible to set k=3. In that case, onegate selection period is divided into a period T0, a period T1, a periodT2, and a period T3. A video signal can be written to the pixel of red(R), the pixel of green (G), and the pixel of blue (B) in the period T1,the period T2, and the period T3, respectively. However, this embodimentis not limited thereto, and the order of the period T1, the period T2,and the period T3 can be set as appropriate.

In specific, in the case where a pixel is divided into n sub-pixels(also referred to as subpixels) (n is a natural number), it is possibleto set k=n. For example, in the case where the pixel is divided into twosub-pixels, it is possible to set k=2. In that case, one gate selectionperiod is divided into the period T0, the period T1, and the period T2.A video signal can be written to one of the two sub-pixels in the periodT1, and a video signal can be written to the other of the two sub-pixelsin the period T2.

Note that since the driving frequency of the circuit 600 and thecircuits 602_1 to 602_N is low in many cases, the circuit 600 and thecircuits 602_1 to 602_N can be formed over the same substrate as a pixelportion. Accordingly, the number of connections between the substrateover which the pixel portion is formed and an external circuit can bereduced; thus, an increase in yield, an improvement in reliability, orthe like can be achieved.

Note that the shift register described in Embodiment 1 or Embodiment 2can be used as the circuit 600. In that case, if all the thin filmtransistors included in the circuit 600 are n-channel transistors, amicrocrystalline semiconductor can be used for a semiconductor layer ofthe thin film transistor. Accordingly, an increase in the size of adisplay device, a reduction in cost, an improvement in yield, or thelike can be achieved. Further, by the use of a microcrystallinesemiconductor for a semiconductor layer, degradation of characteristicsof the thin film transistor can be suppressed, so that the life of adisplay device can be extended.

Note that not only the thin film transistors included in the circuit 600but also all the thin film transistors included in the circuits 602_1 to602_N can be the same conductivity type. Accordingly, when the circuit600 and the circuits 602_1 to 602_N are formed over the same substrateas the pixel portion, a reduction in the number of steps, an increase inyield, or a reduction in cost can be achieved. Further, by the use of amicrocrystalline semiconductor for a semiconductor layer, degradation ofcharacteristics of the thin film transistor can be suppressed, so thatthe life of the display device can be extended.

Note that the contents described in each drawing in this embodiment canbe freely combined with or replaced with the contents described in anyof the other embodiments as appropriate.

Embodiment 5

In this embodiment, structures and operation of pixels which can be usedin a liquid crystal display device are described.

FIG. 15A illustrates an example of a pixel. A pixel 5420 includes a thinfilm transistor 5321, a liquid crystal element 5422, and a capacitor5423. A first terminal of the thin film transistor 5321 is connected toa wiring 5431. A second terminal of the thin film transistor 5321 isconnected to one electrode of the liquid crystal element 5422 and oneelectrode of the capacitor 5423. A gate of the thin film transistor 5421is connected to a wiring 5432. The other electrode of the liquid crystalelement 5422 is connected to an electrode 5434. The other electrode ofthe capacitor 5423 is connected to a wiring 5433.

Note that a liquid crystal element is an element which controlstransmission or non-transmission of light by optical modulation actionof liquid crystals and includes a pair of electrodes and liquidcrystals. Note that the optical modulation action of liquid crystals iscontrolled by an electric field applied to the liquid crystals(including a horizontal electric field, a vertical electric field, and adiagonal electric field). Note that the following can be used for aliquid crystal element: a nematic liquid crystal, a cholesteric liquidcrystal, a smectic liquid crystal, a discotic liquid crystal, athermotropic liquid crystal, a lyotropic liquid crystal, a low-molecularliquid crystal, a high-molecular liquid crystal, a polymer dispersedliquid crystal (PDLC), a ferroelectric liquid crystal, ananti-ferroelectric liquid crystal, a main-chain liquid crystal, aside-chain high-molecular liquid crystal, a plasma addressed liquidcrystal (PALC), a banana-shaped liquid crystal, and the like. Inaddition, the following can be used as a diving method of a liquidcrystal: a TN (twisted nematic) mode, an STN (super twisted nematic)mode, an IPS (in-plane-switching) mode, an FFS (fringe field switching)mode, an MVA (multi-domain vertical alignment) mode, a PVA (patternedvertical alignment) mode, an ASV (advanced super view) mode, an ASM(axially symmetric aligned microcell) mode, an OCB (opticallycompensated birefringence) mode, an ECB (electrically controlledbirefringence) mode, an FLC (ferroclectric liquid crystal) mode, an AFLC(anti-ferroelectric liquid crystal) mode, a PDLC (polymer dispersedliquid crystal) mode, a guest-host mode, a blue phase mode, and thelike.

A video signal is input to the wiring 5431, for example. A scan signal,a selection signal, or a gate signal is input to the wiring 5432, forexample. A constant voltage is applied to the electrode 5433, forexample. A constant voltage is applied to the wiring 5434, for example.Note that this embodiment is not limited to this. A write time of avideo signal can be shortened by supply of precharge voltage to thewiring 5431. Alternatively, voltage applied to the liquid crystalelement 5422 can be controlled by input of a signal to the wiring 5433.Alternatively, frame inversion driving can be realized by input of asignal to the electrode 5434.

Note that the wiring 5431 functions as a signal line, a video signalline, or a source line. The wiring 5432 functions as a signal line, ascan line, or a gate line. The wiring 5433 functions as a power supplyline or a capacitor line. The electrode 5434 functions as a commonelectrode or a counter electrode. The electrode 5434 functions as acommon electrode or a counter electrode. However, this embodiment is notlimited to this. In the case where voltage is supplied to the wiring5431 and the wiring 5432, these wirings function as power supply lines.Alternatively, in the case where a signal is input to the wiring 5433,the wiring 5433 functions as a signal line.

The thin film transistor 5421 has a function of controlling timing whena video signal is written to a pixel by controlling the conduction stateof the wiring 5431 and one electrode of the liquid crystal element 5422,and can function as a switch. The capacitor 5423 has a function ofkeeping voltage applied to the liquid crystal element 5422 as a stablevalue by storing the potential difference between one electrode of theliquid crystal element 5422 and the wiring 5433, and functions as astorage capacitor. Note that this embodiment is not limited to this.

FIG. 15B shows an example of a timing chart showing operation of thepixel in FIG. 15A. FIG. 15B illustrates a signal 5442_j (j is a naturalnumber), a signal 5442_j+1, a signal 5441_i (is a natural number), asignal 5441_i+1, and a voltage 5442. In addition, FIG. 15B illustrates ak-th (k is a natural number) frame and a (k+1)th frame. Note that thesignal 5442_j, the signal 5442_j+1, the signal 5441_1, the signal5441_i+1, and the voltage 5442 are examples of a signal input to thewiring 5432 in a j-th row, a signal input to the wiring 5432 in a(f+1)th row, a signal input to the wiring 5431 in an 1-th column, asignal input to the wiring 5431 in an (i+1)th column, and a voltagesupplied to the wiring 5432, respectively.

Operation of the pixel 5420 in the J-th row and the i-th column isdescribed. When the signal 5442_j is set at an H level, the thin filmtransistor 5421 has electrical continuity between the source and thedrain. Accordingly, the wiring 5431 in the i-th column and one electrodeof the liquid crystal element 5422 are conducting, so that the signal3041_j is input to the one electrode of the liquid crystal element 5422through the thin film transistor 5421. Then, the capacitor 5423 keepsthe potential difference between one electrode of the liquid crystalelement 5422 and the wiring 5433. Thus, after that, a voltage applied tothe liquid crystal element 5422 is constant until the signal 5422_j isset at the H level again. Then, the liquid crystal element 5422expresses gray levels corresponding to the applied voltage.

Note that FIG. 15B shows an example of the case where a positive signaland a negative signal are alternately input to the wiring 5431 everyselection period. A positive signal is a signal whose potential ishigher than a reference value (e.g., a potential of the electrode 5434).A negative signal is a signal whose potential is lower than a referencevalue (e.g., a potential of the electrode 5434). However, thisembodiment is not limited to this, and signals with the same polaritycan be input to the wiring 5431 in one frame period.

Note that FIG. 15B shows an example of the case where the polarity ofthe signal 5441_i and the polarity of the signal 5441_i+1 are differentfrom each other. However, this embodiment is not limited to this. Thepolarity of the signal 5441_i and the polarity of the signal 5441_i+1can be the same.

Note that FIG. 15B shows an example of the case where a period duringwhich the signal 5442_j is at the H level and a period during which thesignal 5442_j+1 is at the H level do not overlap with each other.However, this embodiment is not limited to this. As illustrated in FIG.15C, the period during which the signal 5442_j is at the H level and theperiod during which the signal 5442_j+1 is at the H level can overlapwith each other. In that case, signals of the same polarity arepreferably supplied to the wiring 5431 in one frame period. In thismanner, pixels in a (j+1)th row can be precharged by using the signal5441_j written to pixels in the j-th row. Accordingly, a writing time ofa video signal to a pixel can be shortened. Therefore, a high-definitiondisplay device can be obtained. Alternatively, a display portion of thedisplay device can be made large. Alternatively, since the signals ofthe same polarity are input to the wiring 5431 in one frame period,power consumption can be reduced.

Note that by a combination of a pixel structure shown in FIG. 16A andthe timing chart shown in FIG. 15C, dot inversion driving can beachieved. In the pixel structure in FIG. 16A, a pixel 5420 (i,j) isconnected to a wiring 5431_i. On the other hand, a pixel 5420(i,j+1) isconnected to a wiring 5431_i+1. That is, pixels in the i-th column arealternately connected to the wiring 5431_i and the wiring 5431_i+1row-by-row. In this manner, since a positive signal and a negativesignal are alternately written to the pixels in the I-th columnrow-by-row, dot inversion driving can be achieved. However, thisembodiment is not limited to this. The pixels, which are in the i-thcolumn, of every plural rows (e.g., two rows or three rows) can bealternately connected to the wiring 5431_i and the wiring 5431_i+1.

Note that a sub-pixel structure can be used as the pixel structure.FIGS. 16B and 16C each illustrate a structure of the case where a pixelis divided into two sub-pixels. FIG. 16B shows a sub-pixels structurecalled 1S+2G and FIG. 16C shows a sub-pixel structure called 2S+1G. Asub-pixel 5420A and a sub-pixel 5420B correspond to the pixel 5420. Athin film transistor 5421A and a thin film transistor 5421B correspondto the thin film transistor 5421. A liquid crystal element 5422A and aliquid crystal element 5422B correspond to the liquid crystal element5422. A capacitor 5423A and a capacitor 5423B correspond to thecapacitor 5423. A wiring 5431A and a wiring 5431B correspond to thewiring 5431. A wiring 5432A and a wiring 5432B correspond to the wiring5432.

Here, by a combination of the pixel in this embodiment and any of thestructures described in Embodiments 1 to 4, a variety of advantages canbe obtained. For example, in the case where a sub-pixel structure isemployed for the pixel, the number of signals required for driving adisplay device is increased. Therefore, the number of gate lines orsource lines is increased. As a result, the number of connectionsbetween a substrate over which a pixel portion is formed and an externalcircuit is greatly increased in some cases. However, even if the numberof gate lines is increased, a scan line driver circuit and the pixelportion can be formed over the same substrate, as described inEmbodiment 3. Accordingly, the pixel with the sub-pixel structure can beused without a great increase in the number of connections between thesubstrate over which the pixel portion is formed and the externalcircuit. Alternatively, even if the number of source lines is increased,the use of the source driver in Embodiment 4 can reduce the number ofsource lines. Accordingly, the pixel with the sub-pixel structure can beused without greatly increasing the number of connections between thesubstrate over which the pixel portion is formed and the externalcircuit.

Note that the contents described in each drawing in this embodiment canbe freely combined with or replaced with the contents described in anyof the other embodiments as appropriate.

Embodiment 6

In this embodiment, a method for manufacturing the thin film transistorshown in Embodiment 1 is described with reference to FIGS. 20A to 20C,FIGS. 21A to 21C, FIGS. 22A and 22B, FIGS. 23A to 23C, FIGS. 24A and24B, and FIGS. 25A to 25C.

Here, it is preferable that all the thin film transistors formed overthe same substrate have the same polarity because the number ofmanufacturing steps can be reduced. Therefore, in this embodiment, amethod for manufacturing an n-channel thin film transistor is described.

(Method 1)

First, a process for manufacturing the thin film transistor shown inFIG. 17 is described with reference to FIGS. 20A to 20C. As shown inFIG. 20A, the gate electrode 1103 is formed over the substrate 1101.Next, after the formation of the gate insulating layer 1105 which coversthe gate electrode 1103, a first semiconductor layer 1106 is formed.

The gate electrode 1103 can be formed in such a manner that a conductivelayer is formed over the substrate 1101 with the use of the materialdescribed in Embodiment 1 by sputtering or vacuum evaporation; a mask isformed over the conductive layer by a photolithography technique, aninkjet method, or the like; and the conductive layer is etched with theuse of the mask. Alternatively, the gate electrode 1103 can be formed ina manner that a conductive nanopaste of silver, gold, copper, or thelike is deposited over the substrate by an inkjet method and theconductive nanopaste is baked. Here, the gate electrode 1103 is formedin a way that a conductive layer is formed over the substrate 1101 andthe conductive layer is etched with a resist mask formed with the use ofa photomask.

Note that, in a photolithography step, a resist may be applied to anentire surface over a substrate. Alternatively, a resist is printed by aprinting method on a region in which a resist mask is intended to beformed, and then, the resist is exposed to light, whereby a resist canbe saved, and cost can be reduced. Instead of exposing a resist to lightby using a light-exposure machine, a laser beam direct drawing apparatusmay be used to expose a resist to light.

When side surfaces of the gate electrode 1103 are tapered, disconnectionof the semiconductor layer and the wiring layer formed over the gateelectrode 1103 at a step portion can be prevented. In order that theside surfaces of the gate electrode 1103 be tapered, etching may beperformed while the resist mask is being receded.

Through the step of forming the gate electrode 1103, a gate wiring (ascan line) and a capacitor wiring can also be formed concurrently. Notethat a scan line refers to a wiring for selecting a pixel, and acapacitor wiring refers to a wiring which is connected to one ofelectrodes of a capacitor in a pixel. However, this embodiment is notlimited to this. The gate electrode 1103 and either one or both a gatewiring and a capacitor wiring may be formed separately.

The gate insulating layer 1105 can be formed using the materialdescribed in Embodiment 1 by CVD, sputtering, or the like. In addition,the gate insulating layer 1105 may be formed using a microwaveplasma-enhanced CVD apparatus with a high frequency (1 GHz or higher).When the gate insulating layer 1105 is formed by a microwaveplasma-enhanced CVD apparatus, withstand voltage between a gateelectrode and each of a drain electrode and a source electrode can beimproved. Thus, a highly reliable thin film transistor can be obtained.Further, by forming a silicon oxide layer as the gate insulating layer1105 by CVD using an organosilane gas, the crystallinity of themicrocrystalline semiconductor layer which is formed later can beimproved and the on-state-current and the field-effect mobility of thethin film transistor can be increased. As the organosilane gas, acompound containing silicon, such as tetraethyl orthosilicatetetraethoxysilane (TEOS) (chemical formula: Si(OC₂H₅)₄),tetramethylsilane (TMS) (chemical formula: Si(CH₃)₄),tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane(OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH(OC₂H₅)₃), ortrisdimethylaminosilane (SiH(N(CH₃)₂)₃), can be used.

The first semiconductor layer 1106 is formed using microcrystallinesilicon, microcrystalline silicon germanium, microcrystalline germanium,or the like. The first semiconductor layer 1106 is formed with athickness of 3 nm to 10 nm, preferably 3 nm to 5 nm, so that in a secondsemiconductor layer to be formed in a later process, the length of aplurality of conical or pyramidal projections formed using amicrocrystalline semiconductor can be controlled and on-state-currentand the field-effect mobility of the thin film transistor can beincreased.

The first semiconductor layer 1106 is formed by glow discharge plasmawith a mixture of a deposition gas containing silicon or germanium andhydrogen in a treatment chamber of a plasma-enhanced CVD apparatus.Alternatively, the first semiconductor layer 1106 is formed by glowdischarge plasma with a mixture of a deposition gas containing siliconor germanium, hydrogen, and a rare gas such as helium, neon, or krypton.Microcrystalline silicon, microcrystalline silicon germanium,microcrystalline germanium, or the like is formed using a mixture of thedeposition gas containing silicon or germanium and hydrogen, which isobtained by diluting the deposition gas with hydrogen whose flow rate is10 to 2000 times, preferably 50 to 200 times as high as that of thedeposition gas.

Typical examples of the deposition gas containing silicon or germaniumare SiH₄, Si₂H₆, GeH₄, Ge₂H₆, and the like.

A rare gas such as helium, argon, neon, krypton, or xenon is used as asource gas for the first semiconductor layer 1106, whereby thedeposition rate of the first semiconductor layer 1106 can be increased.In addition, as the deposition rate is increased, the amount ofimpurities mixed in the first semiconductor layer 1106 is reduced; thus,the crystallinity of the first semiconductor layer 1106 can be improved.Accordingly, the on-state-current and field-effect mobility of the thinfilm transistor can be increased and productivity of the thin filmtransistor can also be increased.

When the first semiconductor layer 1106 is formed, glow discharge plasmais generated by application of a high frequency power of 3 to 30 MHz,typically, a high frequency power of 13.56 MHz or 27.12 MHz in the HFband, or a high frequency power of approximately 30 to 300 MHz in theVHF band, typically 60 MHz. Alternatively, glow discharge plasma isgenerated by applying high frequency power of a microwave of 1 GHz orhigher. With the use of high frequency power in the VHF band or at amicrowave frequency, the deposition rate can be increased. In addition,high frequency power in the HF band is superimposed with high frequencypower in the VHF band, whereby unevenness of plasma in a large-sizedsubstrate is also reduced, the uniformity can be increased, and thedeposition rate can be increased.

Note that before the first semiconductor layer 1106 is formed, impurityelements in the treatment chamber of the plasma-enhanced CVD apparatusare removed by introducing a deposition gas containing silicon orgermanium with gas in the treatment chamber exhausted, so that theamount of impurities in the gate insulating layer 1105 and the firstsemiconductor layer 1106 of a thin film transistor to be formed latercan be reduced. Thus, electric characteristics of the thin filmtransistor can be improved.

Next, as shown in FIG. 20B, a semiconductor layer is stacked over thefirst semiconductor layer 1106, so that a second semiconductor layer1107 is formed. Then, an impurity semiconductor layer 1109 and aconductive layer 1111 are formed over the second semiconductor layer1107. After that, a resist mask 1113 is formed over the conductive layer1111.

The second semiconductor layer 1107 including a microcrystallinesemiconductor layer 1107 a, a mixed layer 1107 b, and a layer 1107 cincluding an amorphous semiconductor is formed under a condition thatpart of the crystal region grows with the first semiconductor layer 1106used as a seed crystal. Note that in this case, for convenience, astructure in which the second semiconductor layer 1107 includes thefirst semiconductor layer 1106, that is, a structure in which the firstsemiconductor layer 1106 is included in the microcrystallinesemiconductor layer 1107 a is described.

The second semiconductor layer 1107 is formed by glow discharge plasmawith a mixture of a deposition gas containing silicon or germanium,hydrogen, and a gas containing nitrogen in a treatment chamber of theplasma-enhanced CVD apparatus. As examples of the gas containingnitrogen, there are ammonia, nitrogen, nitrogen fluoride, nitrogenchloride, and the like.

At this time, a condition for forming a microcrystalline semiconductorlayer is used for the flow rate ratio of the deposition gas includingsilicon or germanium to hydrogen in a manner similar to formation of thefirst semiconductor layer 1106, and in addition, the gas includingnitrogen is used for a source gas, whereby crystal growth can be reducedas compared with the case of forming the first semiconductor layer 1106.As a result, the mixed layer 1107 b and the layer 1107 c including anamorphous semiconductor, which is formed with a semiconductor layerhaving a small number of defects and a steep tail slope of a level at aband edge in the valence band, can be formed in the second semiconductorlayer 1107.

Here, a typical example of a condition for forming a microcrystallinesemiconductor layer is as follows: The flow rate ratio of hydrogen is 10to 2000 times, preferably, 10 to 200 times that of the deposition gasincluding silicon or germanium.

A rare gas such as helium, neon, argon, xenon, or krypton is introducedinto a source gas for the second semiconductor layer 1107, whereby thedeposition rate of the second semiconductor layer 1107 can be increased.

In an early stage of deposition of the second semiconductor layer 1107,the first semiconductor layer 1106 serves as a seed crystal and amicrocrystalline semiconductor layer is deposited over the entire areaover the first semiconductor layer 1106 (an early stage of deposition).After that, since the gas containing nitrogen is included in the sourcegas, crystal growth is partially suppressed and conical or pyramidalmicrocrystalline semiconductor region is formed and an amorphoussemiconductor region is formed (a middle stage of the deposition).Further, crystal growth of the conical or pyramidal microcrystallinesemiconductor region stops and a layer including an amorphoussemiconductor is formed (a later stage of the deposition).

Accordingly, the microcrystalline semiconductor layer 1115 a illustratedin FIG. 17 and FIGS. 18A and 18B corresponds to the first semiconductorlayer 1106 in FIG. 20A and a microcrystalline semiconductor layer whichis formed in the early stage of deposition of the second semiconductorlayer 1107, i.e., the microcrystalline semiconductor layer 1107 a inFIG. 20B.

Further, the mixed layers 1115 b illustrated in FIG. 17 and FIGS. 18Aand 18B correspond to a layer which includes the conical or pyramidalmicrocrystalline semiconductor regions and regions filling the spaceexcept the conical or pyramidal microcrystalline regions and is formedin a middle stage of deposition of the second semiconductor layer 1107in FIG. 20B, i.e., the mixed layer 1107 b.

The layer 1129 c including an amorphous semiconductor shown in FIG. 17and FIGS. 18A and 18B corresponds to the layer 1107 c including anamorphous semiconductor, which is formed in a later stage of depositionof the second semiconductor layer 1107 shown in FIG. 20B.

In the second semiconductor layer 1107 formed by such a method, thenitrogen concentration which is measured by secondary ion massspectrometry has a peak in the vicinity of the interface between themicrocrystalline semiconductor layer 1107 a and the mixed layer 1107 band is constant in a direction in which the mixed layer 11076 and thelayer 1107 c including an amorphous semiconductor are deposited.

The impurity semiconductor layer 1109 is formed by glow discharge plasmawith a mixture of a deposition gas containing silicon, hydrogen, andphosphine (diluted with hydrogen or silane) in the treatment chamber ofthe plasma-enhanced CVD apparatus. Amorphous silicon to which phosphorusis added or microcrystalline silicon to which phosphorus is added isformed by diluting the deposition gas including silicon with hydrogen.

The conductive layer 1111 can be formed using a material similar to thatof the wirings 1125 shown in FIG. 17. The conductive layer 1111 isformed by CVD, sputtering, or vacuum evaporation. Alternatively, theconductive layer 1111 may be formed by discharging a conductivenanopaste of silver, gold, copper, or the like by a screen printingmethod, an inkjet method, or the like and baking the conductivenanopaste.

The second resist mask 1113 is formed by a photolithography process. Thesecond resist mask 1113 has regions with different thicknesses. Such aresist mask can be formed using a multi-tone mask. By using themulti-tone mask, the number of photomasks used and the number ofmanufacturing steps can be reduced, which is preferable. In thisembodiment, the multi-tone mask can be used in a step of forming apattern of the second semiconductor layer 1107 and a step of separatingthe semiconductor layer into a source region and a drain region.

A multi-tone mask is a mask capable of light exposure with multi-levellight intensity, typically, with three levels of light intensity so thatan exposed region, a semi-exposed region, and an unexposed region areformed. With the use of the multi-tone mask, a resist mask with pluralthicknesses (typically two kinds of thicknesses) can be formed byone-time exposure and a development process. Therefore, with the use ofthe multi-tone mask, the number of photomasks can be reduced.

FIGS. 22A-I and 22B-1 are cross-sectional views of typical multi-tonemasks. FIG. 22A-1 shows a gray-tone mask 1180, and FIG. 22B-1 shows ahalf-tone mask 1185.

The gray-tone mask 1180 shown in FIG. 22A-1 includes a light-blockingportion 1182 formed using a light-blocking layer on a light-transmittingsubstrate 1181, and a diffraction grating portion 1183 provided with apattern of the light-blocking layer.

The diffraction grating portion 1183 has slits, dots, meshes, or thelike provided at intervals which are less than or equal to theresolution limit of light used for exposure, so that light transmittanceis controlled. Note that the slits, dots, or meshes provided at thediffraction grating portion 1183 may be provided periodically ornon-periodically.

For the light-transmitting substrate 1181, quartz or the like can beused. The light-blocking layer included in the light-blocking portion182 and the diffraction grating portion 1183 is formed using chromium,chromium oxide, or the like.

In the case where the gray-tone mask 1180 is irradiated with light forexposure, as shown in FIG. 22A-2, transmittance in a region overlappingwith the light-blocking portion 1182 is 0%, and transmittance in aregion where the light-blocking portion 1182 or the diffraction gratingportion 183 is not provided is 100%. Further, transmittance at thediffraction grating portion 1183 is approximately in the range of 10 to70%, which can be adjusted by the interval of slits, dots, or meshes ofthe diffraction grating, or the like.

The half-tone mask 1185 shown in FIG. 22B-1 includes asemi-light-transmitting portion 1187 formed using asemi-light-transmitting layer on a light-transmitting substrate 1186,and a light-blocking portion 1188 formed using a light-blocking layer.

The semi-light-transmitting portion 1187 can be formed using a layer ofMoSiN, MoSi, MoSiO, MoSiON, CrSi, or the like. The light-blockingportion 1188 may be formed using a metal which is similar to that of thelight-blocking layer of the gray-tone mask, and is preferably formedusing chromium, chromium oxide, or the like.

In the case where the half-tone mask 1185 is irradiated with light forexposure, as illustrated in FIG. 22B-2, transmittance in a regionoverlapping with the light-blocking portion 1188 is 0%, andtransmittance in a region where neither the light-blocking portion 1188nor the semi-light-transmitting portion 1187 is provided is 100%.Further, transmittance at the semi-light-transmitting portion 1187 isapproximately in the range of 10 to 70%, which can be adjusted by thekind, thickness, or the like of a material to be used.

By performing exposure using the multi-tone mask and development, aresist mask having regions with different thicknesses can be formed.

Next, with the use of the second resist mask 1113, the secondsemiconductor layer 1107, the impurity semiconductor layer 1109, and theconductive layer 1111 are etched. Through this step, the secondsemiconductor layer 1107, the impurity semiconductor layer 1109, and theconductive layer 1111 are separated into each element to form a secondsemiconductor layer 1115, an impurity semiconductor layer 1117, and aconductive layer 1119. Note that the second semiconductor layer 1115includes the microcrystalline semiconductor layer 1115 a, the mixedlayer 1115 b, and a layer 1115 c including an amorphous semiconductor(see FIG. 20C).

Next, separated third resist masks 1123 are formed with the secondresist mask 1113 eroded. Ashing using oxygen plasma may be performed inorder that the resist mask recede. Here, ashing is performed on thesecond resist mask 1 s 13 so that the resist mask 1113 is separated overthe gate electrode. Thus, the third resist masks 1123 can be formed (seeFIG. 21A).

Next, the conductive layer 1111 is etched using the third resist masks1123, so that the wirings 1125 functioning as a source electrode and adrain electrode are formed (see FIG. 21B). It is preferable that theconductive layer 1111 be removed by wet etching. By wet etching, theconductive layer is isotropically etched. Accordingly, the conductivelayer recedes to an inner side than those of the resist masks 1123, sothat the wirings 1125 are formed. The wiring 1125 functions not only asa source electrode or a drain electrode but also as a signal line.However, this embodiment is not limited to this. The signal line may beprovided separately from the source electrode and the drain electrode.

Next, with the use of the third resist masks 1123, the layer 1115 cincluding an amorphous semiconductor and the impurity semiconductorlayer 1117 are partly etched. Here, dry etching is used. Up to thisstep, an amorphous semiconductor layer 1129 c having a depression on itssurface, and the impurity semiconductor layers 1127 functioning as asource and drain regions are formed. After that, the third resist masks1123 are removed (see FIG. 21C).

Note that, here, after the conductive layer 1111 is etched by wetetching, each of the layer 1115 c including an amorphous semiconductorand the impurity semiconductor layer 1117 is partly etched by dryetching. Thus, the conductive layer 1119 is isotropically etched, andside surfaces of the wirings 1125 are not aligned with side surfaces ofthe impurity semiconductor layers 1127. That is, the side surfaces ofthe impurity semiconductor layers 1127 are formed on an outer side thanthe side surfaces of the wirings 1125.

Alternatively, the impurity semiconductor layer 1117 and the layers 1115c including an amorphous semiconductor may be partly etched afterremoval of the third resist masks 1123. By the etching, the impuritysemiconductor layer 1117 is etched using the wirings 1125, so that theside surfaces of the wirings 1125 are approximately aligned with theside surfaces of the impurity semiconductor layers 1127.

Next, dry etching may be performed after the third resist masks 1123 areremoved. The condition of dry etching is set so that the exposed layer1129 c including an amorphous semiconductor is not damaged and anetching rate with respect to the layer 1129 c including an amorphoussemiconductor is low. In other words, a condition which gives almost nodamages to the exposed layer 1129 c including an amorphous semiconductorand hardly reduces the thickness of the exposed layer 1129 c includingan amorphous semiconductor is used. As an etching gas, C12, CF₄, N₂, orthe like is typically used. Further, there is no particular limitationon an etching method, and an inductively coupled plasma (ICP) method, acapacitively coupled plasma (CCP) method, an electron cyclotronresonance (ECR) method, a reactive ion etching (RIE) method, or the likecan be used.

Next, a surface of layer 1129 c including an amorphous semiconductorcontaining an amorphous semiconductor may be irradiated with waterplasma, ammonia plasma, nitrogen plasma, or the like.

Water plasma treatment can be performed in such a manner that a gascontaining water as a main component typified by water vapor (H₂O vapor)is introduced into a reaction space so that plasma is generated.

As described above, dry etching is further performed under a conditionwhere the layer 1129 c including an amorphous semiconductor is notdamaged after the impurity semiconductor layers 1127 are formed, so thatan impurity element such as a residue existing on the exposed layer 1129c including an amorphous semiconductor can be removed. Further, waterplasma treatment is performed after the dry etching, so that a residueof the resist mask can be removed. By the water plasma treatment,insulation between the source region and the drain region can beensured. Thus, in a thin film transistor which is completed, the amountof off-state current can be reduced, and variation in electriccharacteristics can be reduced.

Through these steps, a thin film transistor with a channel region formedusing a microcrystalline semiconductor layer can be manufactured withthe use of fewer masks. Further, the thin film transistor having a smallamount of off-state-current, a large amount of on-state-current, andhigh field-effect mobility can be manufactured.

(Method 2)

A method for manufacturing a thin film transistor, which is differentfrom in Method 1, is described with reference to FIGS. 20A to 20C, FIGS.23A to 23C, and FIGS. 24A and 24B.

In a manner similar to Method 1, the gate electrode 1103 is formed overthe substrate 1101. Next, the gate insulating layer 1105 and the firstsemiconductor layer 1106 are formed so as to cover the gate electrode1103 (see FIG. 20A). Then, in a manner similar to Method 1, crystals aregrown from the first semiconductor layer 1106, whereby the secondsemiconductor layer 1107 including (the microcrystalline semiconductorlayer 1107 a, the mixed layer 1107 b, and the layer 1107 c including anamorphous semiconductor) is formed. Then, the impurity semiconductorlayer 1109 is formed over the second semiconductor layer 1107 (see FIG.23A). After that, a resist mask (not shown) is formed over the impuritysemiconductor layer 1109.

Next, with the use of the resist mask, the second semiconductor layer1107 and the impurity semiconductor layer 1109 are etched. Through thisstep, the second semiconductor layer 1107 and the impurity semiconductorlayer 1109 are separated into each element, so that the secondsemiconductor layer 1115 (including the microcrystalline semiconductorlayer 1115 a, the mixed layer 1115 b, and the layer 1115 c including anamorphous semiconductor) and the impurity semiconductor layer 1117 areformed (see FIG. 23B).

Next, the conductive layer 1111 is formed over the gate insulating layer1105, the second semiconductor layer 1115, and the impuritysemiconductor layer 1117 (see FIG. 23C).

Next, a resist mask (not shown) is formed over the conductive layer1111, and the conductive layer 1111 is etched with the use of the resistmask, so that wirings 1133 functioning as a source and drain electrodesare formed (see FIG. 24A).

Next, the impurity semiconductor layer 1117 is etched so that theimpurity semiconductor layers 1127 functioning as a source and drainregions are formed. Further, the layer 1115 c including an amorphoussemiconductor is etched so that the layer 1129 c including an amorphoussemiconductor is formed (see FIG. 24B).

Through the above steps, the thin film transistor can be manufactured.

Note that the layer 1115 including an amorphous semiconductor is partlyetched without removal of the resist mask after forming the wirings1133; however, part of the impurity semiconductor layer 1117 and part ofthe layer 1129 c including an amorphous semiconductor may be etchedafter removal of the resist mask. By the etching, the impuritysemiconductor layer 1117 is etched using the wirings 1133 as masks, sothat side surfaces of the wirings 1133 are approximately aligned withside surfaces of the impurity semiconductor layers 1127.

Next, dry etching is preferably performed after the resist mask isremoved. The condition of dry etching is set so that the exposed layer1129 c including an amorphous semiconductor is not damaged and anetching rate with respect to the layer 1129 c including an amorphoussemiconductor is low. In other words, a condition that a surface of theexposed layer 1129 c including an amorphous semiconductor is hardlydamaged and the thickness of the exposed layer 1129 c including anamorphous semiconductor is hardly decreased is used.

Next, the surface of the layer 1129 c including an amorphoussemiconductor may be irradiated with water plasma, ammonia plasma,nitrogen plasma, or the like.

Water plasma treatment can be performed in such a manner that a gascontaining water as a main component typified by water vapor (H₂O vapor)is introduced into a reaction space so that plasma is generated.

As described above, dry etching is further performed under a conditionwhere the layer 1129 c including an amorphous semiconductor is notdamaged after the layer 1129 c including an amorphous semiconductor isformed, so that an impurity element such as a residue existing on thelayer 1129 c including an amorphous semiconductor can be removed.Further, water plasma treatment is performed after the dry etching, sothat a residue of the resist mask can be removed. By the water plasmatreatment, insulation between the source region and the drain region canbe ensured. Thus, in a thin film transistor, the amount of off-statecurrent can be reduced, and variation in electric characteristics can bereduced.

(Method 3)

Next, a method for manufacturing the thin film transistor shown in FIG.19 is described with reference to FIGS. 20A to 20C, FIGS. 21A to 21C,and FIGS. 25A to 25C.

In a manner similar to Method 1, after the wirings 1125 are formedthrough the steps in FIGS. 20A to 20C, FIG. 21A, and FIG. 21B, theimpurity semiconductor layer 1117 is etched so that the impuritysemiconductor layers 1127 are formed. Further the layer 1115 c includingan amorphous semiconductor is etched so that a pair of layers 1132including an amorphous semiconductor is formed (see FIG. 25A).

Here, a condition is used as appropriate under which the layer 1115 cincluding an amorphous semiconductor is selectively etched by wetetching or dry etching so that the second microcrystalline semiconductorlayer 1131 b is exposed. As a typical example of an etchant whichenables wet etching whereby an amorphous semiconductor layer canselectively be etched, an etchant including hydrazine, potassiumhydroxide, or ethylenediamine can be used. Alternatively, an etchantincluding a mixed solution of hydrofluoric acid and nitric acid can beused. Alternatively, a tetramethyl ammonium hydroxide (also referred toas TMAH) aqueous solution can be used.

In addition, hydrogen can be used as an etching gas which enables dryetching whereby an amorphous semiconductor layer can selectively beetched. Alternatively, a gas containing chlorine, bromine, or iodine canbe used as the etching gas. As typical example, hydrogen chloride,hydrogen bromide, hydrogen iodide, silicon tetrachloride, phosphorustrichloride, boron trichloride or the like can be used. Alternatively, agas containing fluorine can be used as the etching gas. As a typicalexample, tetrafluoromethane, sulfur hexafluoride, nitrogen trifluoride,silicon tetrafluoride, boron trifluoride, xenon difluoride, chlorinetrifluoride, or the like can be used. Alternatively, a mixed gas oftetrafluoromethane and oxygen, or a mixed gas of sulfur hexafluoride andchlorine can be used as the etching gas.

After that, a resist mask is removed, and plasma treatment 1140 by whichsurfaces of the second microcrystalline semiconductor layer 1131 b, thepair of layers 1132 including an amorphous semiconductor, the impuritysemiconductor layers 1127, and the wirings 1125 is oxidized or nitridedis performed, whereby the first insulating layer 1135 a, the secondinsulating layers 1135 c, and the third insulating layers 1135 e shownin FIG. 25C are formed.

The pair of layers 1132 include an amorphous semiconductor and thus havea weak n-type conductivity. In addition, the pair of layer 1132including an amorphous semiconductor has lower density than themicrocrystalline semiconductor layer 1131. Therefore, the secondinsulating layers 1135 c formed by oxidizing or nitriding the pair oflayers 1132 including an amorphous semiconductor is insulating layershaving low density and low insulating property. However, in the thinfilm transistor shown in FIG. 19, the first insulating layer 1135 aformed by oxidizing the microcrystalline semiconductor layer 1131 isformed on a back channel side. The microcrystalline semiconductor layerhas higher density than the amorphous semiconductor layer, and the firstinsulating layer 1135 a thus has also high density and a high insulatingproperty. Further, the second insulating layer 1131 b has a plurality ofconical or pyramidal protrusions (projections) and thus has an unevensurface. Therefore, a leak path between a source region and a drainregion has a long distance. Accordingly, a reduction inoff-state-current of the thin film transistor can be realized.

Note that here, after the wirings 1125 are formed, the layer 1115 cincluding an amorphous semiconductor is etched so that the secondmicrocrystalline semiconductor layer 1131 b is exposed. However, thefollowing may be performed. The wirings 1125 are formed; the resist maskis removed; each of the impurity semiconductor layer 1117 and the layer1115 c including an amorphous semiconductor is partly etched by dryetching; and the plasma treatment 1140 by which the surface of thesecond microcrystalline semiconductor layer 1131 b is oxidized ornitrided is performed. In that case, since the impurity semiconductorlayer 1127 and the layer 1115 c including an amorphous semiconductor areetched using the wirings 1125 as masks, side surfaces of the wirings1125 are approximately aligned with side surfaces of the impuritysemiconductor layers 1127.

As described above, after the second microcrystalline semiconductorlayer 1131 b having conical or pyramidal protrusions (projections) isexposed, an insulating layer is formed on the surface of the secondmicrocrystalline semiconductor layer 1131 b by plasma treatment; thus, aleak path between the source region and the drain region can have a longdistance, and an insulating layer having a high insulating property canbe formed.

(Method 4)

A method for manufacturing the second semiconductor layer 1107, whichcan be applied to any of Methods 1 to 3, is described below. In thiscase, instead of using the gas containing nitrogen as the source gas ofthe second semiconductor layer 1107, by forming the second semiconductorlayer 1107 after forming a layer containing nitrogen in a treatmentchamber of the plasma-enhanced CVD apparatus, the second semiconductorlayer 1107 can be supplied with nitrogen.

After the first semiconductor layer 1106 is formed, the substrate iscarried out of the treatment chamber of the plasma-enhanced CVDapparatus. Next, a layer containing nitrogen is formed in the treatmentchamber of the plasma-enhanced CVD apparatus. In this case, as the layercontaining nitrogen, a silicon nitride layer is formed. Then, after thesubstrate is carried into the treatment chamber, a source gas used fordeposition of the second semiconductor layer 1107 is introduced into thetreatment chamber, and the second semiconductor layer 1107 is formed. Inthis case, a deposition gas including silicon or germanium, and hydrogenare used as a source gas. The layer containing nitrogen formed on theinner wall of the treatment chamber is exposed to plasma, whereby partof the layer containing nitrogen is dissociated and nitrogen isdesorbed. Alternatively, an NH group is generated. As a result, thesecond semiconductor layer 1107 contains nitrogen, so that the secondsemiconductor layer 1107 including the microcrystalline semiconductorlayer 1107 a, the mixed layer 1107 b, and the layer 1107 c including anamorphous semiconductor can be formed as shown in FIG. 18A.Alternatively, as shown in FIG. 18B, the second semiconductor layer 1107including the microcrystalline semiconductor layer 1107 a and the mixedlayer 1107 b can be formed.

In the second semiconductor layer 1107 formed by such a method, thenitrogen concentration which is measured by secondary ion massspectrometry has a peak at an upper portion of the microcrystallinesemiconductor layer 1107 a, or in the vicinity of the interface betweenthe microcrystalline semiconductor layer 1107 a and the mixed layer 1107b, and is decreased with respect to a direction in which the secondsemiconductor layer 107 is deposited.

Through the steps above, the second semiconductor layer 1107 can beformed.

(Method 5)

A method for manufacturing the second semiconductor layer 1107, whichcan be applied to any of Methods 1 to 3, is described below. In thiscase, instead of using the gas containing nitrogen as the source gas ofthe second semiconductor layer 1107, by forming the second semiconductorlayer 1107 after introducing a gas containing nitrogen in the treatmentchamber of the plasma-enhanced CVD apparatus before forming the secondsemiconductor layer 1107, the second semiconductor layer 1107 can besupplied with nitrogen.

After the first semiconductor layer 1106 is formed, the surface of thefirst semiconductor layer 1106 is exposed to the gas containing nitrogen(here, this treatment is referred to as flush treatment), so thatnitrogen is supplied to the treatment chamber of the plasma-enhanced CVDapparatus. As examples of the gas containing nitrogen, ammonia,nitrogen, nitrogen fluoride, nitrogen chloride, and the like can begiven. In addition, hydrogen may be included in any of the gascontaining nitrogen. In this case, the surface of the firstsemiconductor layer 1106 is exposed to ammonia, whereby nitrogen issupplied.

Then, after a source gas used for deposition of the second semiconductorlayer 1107 is introduced into the treatment chamber, the secondsemiconductor layer 1107 is formed. In this case, a deposition gasincluding silicon or germanium, and hydrogen are used as a source gas.

In the formation step of the second semiconductor layer 1107, a gascontaining nitrogen introduced into the treatment chamber by the flushtreatment, in this case, ammonia is decomposed by plasma discharge, sothat nitrogen is desorbed. Alternatively, an NH group is generated. As aresult, the second semiconductor layer 1107 contains nitrogen, so thatthe second semiconductor layer 1107 including the microcrystallinesemiconductor layer 1107 a, the mixed layer 1107 b, and the layer 1107 cincluding an amorphous semiconductor can be formed as shown in FIG. 18A.Alternatively, as shown in FIG. 18B, the second semiconductor layer 1107including the microcrystalline semiconductor layer 1107 a and the mixedlayer 1107 can be formed.

In the second semiconductor layer 1107 formed by such a method, thenitrogen concentration which is measured by secondary ion massspectrometry has a peak at an upper portion of the microcrystallinesemiconductor layer 1107 a or in the vicinity of the interface betweenthe microcrystalline semiconductor layer 1107 a and the mixed layer 1107b and is decreased with respect to a direction in which the mixed layer1107 b and the layer 1107 c including an amorphous semiconductor aredeposited.

Through the steps above, the second semiconductor layer 1107 can beformed.

In this embodiment, examples of methods for manufacturing a thin filmtransistor included in a display device are described. Such a structurecan be combined with any of the shift registers in Embodiments 1 to 5.In the case where a microcrystalline semiconductor is used for a channelregion of the thin film transistor, an increase in the size of thedisplay device, a reduction in cost, an improvement in yield, or thelike can be achieved. Further, by the use of a microcrystallinesemiconductor for the channel legion, degradation of characteristics ofthe thin film transistor can be suppressed, so that the life of thedisplay device can be extended.

Note that the contents described in each drawing in this embodiment canbe freely combined with or replaced with the contents described in anyof the other embodiments as appropriate.

Embodiment 7

In this embodiment, as an embodiment of a display device, across-sectional structure of a liquid crystal display device isdescribed with reference to FIGS. 26A and 26B. Specifically, thestructure of a liquid crystal display device which includes a thin filmsubstrate, a counter substrate, and a liquid crystal layer held betweenthe counter substrate and the TFT substrate is described. FIG. 26A is atop view of the liquid crystal display device. FIG. 26B is across-sectional view taken along line C-D in FIG. 26A. Note that FIG.26B is a cross-sectional view of a liquid crystal display device wherean inverted staggered transistor including a microcrystallinesemiconductor in the channel region is formed over a substrate 1601, andthe display mode of the liquid crystal display device is an MVA(multi-domain vertical alignment) mode.

In the liquid crystal display device illustrated in FIG. 26A, a pixelportion 1603, a first scan line driver circuit 1605 a, a second scanline driver circuit 1605 b, and a signal line driver circuit 1607 areformed over the substrate 1601. The pixel portion 1603, the first scanline driver circuit 1605 a, the second scan line driver circuit 1605 b,and the signal line driver circuit 1607 are scaled between the substrate1601 and a substrate 1611 with a sealant 1609. In addition, an FPC 1613and an IC chip 1615 are provided over the substrate 1601 by a TABmethod.

A cross-sectional structure taken along line C-D in FIG. 26A isdescribed with reference to FIG. 26B. In this case, the pixel portion1603, the scan line driver circuit 1605 b which is part of a peripheraldriver circuit portion, and a terminal portion 1617, which are formedover the substrate 1601, are shown.

A thin film transistor 1621 to be provided in the second scan linedriver circuit 1605 b and a thin film transistor 1623 to be provided inthe pixel portion 1603 are formed over the substrate 1601. Further,insulating layers 1625 and 1627 are formed over the thin filmtransistors 1621 and 1623. Furthermore, a wiring 1629 to be connected toa source electrode or a drain electrode of the thin film transistor 1621through an opening portion in the insulating layer 1625 and a pixelelectrode 1631 to be connected to a source electrode or a drainelectrode of the thin film transistor 1623 through an opening portion inthe insulating layer 1625 are formed. Moreover, an insulating layer 1635is formed over the insulating layer 1627, the wiring 1629, and the pixelelectrode 1631.

The contents described in Embodiments 1 to 6 can be applied to eachstructure of the thin film transistors 1621 and 1623 a and a method formanufacturing the thin film transistors 1621 and 1623 as appropriate.

Each of the insulating layer 1625 and the insulating layer 1627 can beformed using an inorganic insulating layer, an organic resin layer, orthe like. As an inorganic insulating layer, a silicon oxide layer, asilicon oxynitride layer, a silicon nitride oxide layer, or a carbonlayer typified by diamond like carbon (DLC), or the like can be used.For an organic resin layer, an acrylic resin, an epoxy resin, polyimide,polyamide, polyvinyl phenol, benzocyclobutene, or the like can be used.Alternatively, a siloxane polymer can be used.

The insulating layer 1625 and the insulating layer 1627 can be formed byCVD, sputtering, a printing method, a coating method, a slit-coatingmethod, or the like as appropriate.

Since at least one of the insulating layer 1625 and the insulating layer1627 is formed using an organic resin layer, planarity can be improved;thus, alignment of liquid crystal molecules can easily be controlled.

The wiring 1629 and the pixel electrode 1631 can be formed using indiumoxide containing tungsten oxide, indium zinc oxide containing tungstenoxide, indium oxide containing titanium oxide, indium tin oxidecontaining titanium oxide, indium tin oxide, indium zinc oxide, indiumtin oxide to which silicon oxide is added, or the like.

Alternatively, the wiring 1629 and the pixel electrode 1631 can beformed using a conductive composition containing a light-transmittingconductive high molecule (also referred to as a conductive polymer).Each of the wiring 1629 and the pixel electrode 1631 preferably has asheet resistance less than or equal to 10000 ohms/square and a lighttransmittance greater than or equal to 70% at a wavelength of 550 nm.The sheet resistance of each of the wiring 1629 and the pixel electrode1631 is preferably lower. In addition, it is preferable that theresistivity of the conductive high molecule contained in the conductivecomposition be 0.1 ohm·cm or less.

As the conductive high molecule, a so-called n electron conjugatedconductive high molecule can be used. For example, polyaniline or aderivative thereof, polypyrrole or a derivative thereof, polythiopheneor a derivative thereof, a copolymer of two or more kinds of them, orthe like can be used.

Note that when the pixel electrode 1631 functions as a reflectiveelectrode, the pixel electrode 1631 can be formed using aluminum,silver, or the like; or an alloy thereof, or the like. In addition, atwo-layer structure of aluminum and titanium, molybdenum, tantalum,chromium, or tungsten; or a three-layer structure in which aluminum isinterposed between any of metals such as titanium, molybdenum, tantalum,chromium, or tungsten may be employed.

An opening portion is formed in the pixel electrode 1631. The openingportion formed in the conductive film can have the same function as aprotrusion used in an MVA mode because the opening portion can makeliquid crystal molecules slanted.

The insulating layer 1635 functions as an alignment film.

The sealant 1609 is formed around the pixel portion 1603, or around thepixel portion 1603 and the peripheral driver circuit portion thereof byan inkjet method or the like. The substrate 1611 on which a conductivelayer 1641, an insulating layer 1643, a protrusion 1645, and the likeare formed and the substrate 1601 are attached to each other with thesealant 1609 with a spacer 1647 interposed therebetween, and a liquidcrystal layer 1649 is provided between the two substrates. Note that thesubstrate 1611 functions as a counter substrate.

The spacer 1647 may be formed in a manner that particles of severalmicrometers are dispersed or in a manner that a resin layer is formedover the entire surface of the substrate and then etched.

The conductive layer 1641 functions as a counter electrode. Theconductive layer 1641 can be formed using a material similar to that ofthe wiring 1629 or the pixel electrode 1631. In addition, the insulatinglayer 1643 functions as an alignment film.

In the terminal portion 1617, a connection terminal 1659 is formed. Theconnection terminal 1659 is electrically connected to the pixel portion1603 and a wiring 1655 in the peripheral driver circuit portion. Theconnection terminal 1659 is formed in a manner similar to those in thepixel electrode 1631 in the pixel portion 1603 and the wiring 1629 inthe peripheral driver circuit portion.

In this case, the thin film transistors 1621 and 1623 are formed throughthe steps with the multi-tone mask; therefore, a microcrystallinesemiconductor layer 1651 which is formed concurrently withmicrocrystalline semiconductor layers of the thin film transistors andan impurity semiconductor layer 1653 which is formed concurrently withsource regions and drain regions are formed between the wiring 1655 andthe substrate 1601.

The FPC 1613 is provided over the connection terminal 1659 with ananisotropic conductive layer 1657 interposed therebetween. Further, theIC chip 1615 is provided over the FPC 1613 with an anisotropicconductive layer 1661 interposed therebetween. That is, the FPC 1613,the anisotropic conductive layers 1657 and 1661, and the IC chip 1615are electrically connected to each other.

An adhesive material such as an ACF (anisotropic conductive film) or ACP(anisotropic conductive paste) can be used for the anisotropicconductive layers 1657 and 1661. In addition, a conductive adhesive suchas silver paste, copper paste, or carbon paste, solder joint, or thelike can be used for the anisotropic conductive layers 1657 and 1661.

Note that by forming a functional circuit (e.g., a memory or a buffer)in the IC chip 1615, the area of the substrate can be efficientlyutilized.

Note that although the cross-sectional view in the case where thedisplay mode is the MVA mode is described in FIG. 26B, the display modemay be a PVA (patterned vertical alignment) mode. In the case of the PVAmode, a slit may be provided for the conductive layer 1641 formed on thesubstrate 1611, so that liquid crystal molecules can be slanted to bealigned. In addition, the protrusion 1645 (also referred to as thealignment control protrusion) may be provided for the conductive filmfor which the slit is provided, so that liquid crystal molecules can beslanted to be aligned. Further, the display mode of liquid crystals isnot limited to the MVA mode or the PVA mode, and a TN (twisted nematic)mode, an IPS (in-plane-switching) mode, an FFS (fringe field switching)mode, an ASM (axially symmetric aligned micro-cell) mode, an OCB(optical compensated birefringence) mode, an FLC (ferroelectric liquidcrystal) mode, an AFLC (antiferroelectric liquid crystal) mode, or thelike can be used.

Although the structure is described in which the first scan line drivercircuit 1605 a, the second scan line driver circuit 1605 b, and thesignal line driver circuit 1607 are formed over the substrate 1601 inthe liquid crystal panel in FIGS. 26A and 26B, a structure may be usedin which a driver circuit corresponding to the signal line drivercircuit 1607 is formed as a driver IC and is mounted on a liquid crystalpanel by COG or the like, as illustrated in FIG. 13B. By forming thesignal line driver circuit 1607 as the driver IC, power can be saved. Inaddition, by forming the driver IC as a semiconductor chip formed usinga silicon wafer or the like, high speed operation and low powerconsumption of the liquid crystal panel can be achieved.

In this embodiment, an example of a cross-sectional structure of thedisplay device is described. Such a structure can be combined with anyof the shift registers in Embodiments 1 to 5. In the case where amicrocrystalline semiconductor is used for a channel region of the thinfilm transistor, an increase in the size of the display device, areduction in cost, an improvement in yield, or the like can be achieved.Further, by the use of a microcrystalline semiconductor for asemiconductor layer, degradation of characteristics of the thin filmtransistor can be suppressed, so that the life of the display device canbe extended.

Note that the contents described in each drawing in this embodiment canbe freely combined with or replaced with the contents described in anyof the other embodiments as appropriate.

Embodiment 8

In this embodiment, examples of electronic devices are described.

A display device according to any of the above embodiments can be usedin a variety of electronic devices (including an amusement machine).Examples of electronic devices are a television set (also referred to asa television or a television receiver), a monitor of a computer,electronic paper, a camera such as a digital camera or a digital videocamera, a digital photo frame, a mobile phone handset (also referred toas a mobile phone or a mobile phone device), a portable game machine, aportable information terminal, an audio reproducing device, a large gamemachine such as a pinball machine, and the like.

Electronic paper which is one embodiment of the display device accordingto any of the above embodiments can be used in electronic devices in allfields as long as they display information. For example, electronicpaper can be used in an electronic book (e-book) reader, a poster, anadvertisement in a vehicle such as a train, display of a variety ofcards such as credit cards, or the like. FIG. 27A illustrates an exampleof an electronic device.

FIG. 27A illustrates an example of an e-book reader. The e-book readerillustrated in FIG. 27A includes two housings 1700 and 1701. Thehousings 1700 and 1701 are combined with each other with a hinge 1704,so that the e-book reader can be opened and closed. With such astructure, the e-book reader can be operated like a paper book.

A display portion 1702 is incorporated in the housing 1700, and adisplay portion 1703 is incorporated in the housing 1701. The displayportions 1702 and 1703 may display a series of images or differentimages. In the case where the display portion 1702 and 1703 displaydifferent images, for example, a display portion on the right side (thedisplay portion 1702 in FIG. 27A) can display text and a display portionon the left side (the display portion 1703 in FIG. 27A) can displayimages.

FIG. 27A illustrates an example in which the housing 1700 includes anoperation portion and the like. For example, the housing 1700 includes apower input terminal 1705, operation keys 1706, a speaker 1707, and thelike. With the operation keys 1706, pages can be turned. Note that akeyboard, a pointing device, or the like may be provided on a surface ofthe housing, on which the display portion is provided. Further, anexternal connection terminal (e.g. an earphone terminal, a USB terminal,or a terminal which can be connected to a variety of cables such as USBcables), a recording medium insertion portion, or the like may beprovided on a back surface or a side surface of the housing.Furthermore, the e-book reader illustrated in FIG. 27A may serve as anelectronic dictionary.

Further, the e-book reader illustrated in FIG. 27A may transmit andreceive data wirelessly. Through wireless communication, data related toa desired book or the like can be purchased and downloaded from anelectronic book server.

FIG. 27B shows an example of a digital photo frame using a displaydevice such as electronic paper, a liquid crystal display device, or alight-emitting display device. For example, in the digital photo frameillustrated in FIG. 27B, a display portion 1712 is incorporated in ahousing 1711. The display portion 1712 can display a variety of images.For example, the display portion 1712 can display data related to imagesphotographed by a digital camera or the like, so that the digital photoframe can function as a normal photo frame.

Note that the digital photo frame illustrated in FIG. 27B includes anoperation portion, an external connection portion (e.g., a USB terminalor a terminal which can be connected to a variety of cables such as USBcables), a recording medium insertion portion, and the like. Althoughthey may be provided on a surface on which the display portion isprovided, it is preferable to provide them on a side surface or a backsurface because the design of the digital photo frame is improved. Forexample, a memory which stores data related to images photographed by adigital camera is inserted in the recording medium insertion portion ofthe digital photo frame, so that the data related to the images can beloaded to the digital photo frame and can be displayed on the displayportion 1712.

Further, the digital photo frame illustrated in FIG. 27B may transmitand receive data wirelessly. Through wireless communication, datarelated to desired images can be loaded and displayed.

FIG. 27C shows an example of a television set in which a display devicesuch as a liquid crystal display device or a light-emitting displaydevice is used. In the television set illustrated in FIG. 27C, a displayportion 1722 is incorporated in a housing 1721. The display portion 1722can display images. Further, here, the housing 1721 is supported by astand 1723. The display device described in any of the above embodimentscan be used in the display portion 1722.

The television set illustrated in FIG. 27C can be operated by anoperation switch of the housing 1721 or a separate remote controller.Channels and volume can be controlled by operation keys of the remotecontroller, so that images displayed on the display portion 1722 can becontrolled. Further, the remote controller may include a display portionfor displaying data output from the remote controller.

Note that the television set illustrated in FIG. 27C includes areceiver, a modem, and the like. With the receiver, a general televisionbroadcast can be received. Further, by connecting the television set toa wired or wireless communication network via the modem, one-way (from atransmitter to a receiver) or two-way (between a transmitter and areceiver, between receivers, or the like) information communication canbe performed.

FIG. 27D shows an example of a mobile phone handset in which a displaydevice such as electronic paper, a liquid crystal display device, or alight-emitting display device is used. The mobile phone handsetillustrated in FIG. 27D includes a display portion 1732 incorporated ina housing 1731, operation buttons 1733 and 1737, an external connectionport 1734, a speaker 1735, a microphone 1736, and the like.

The display portion 1732 of the mobile phone handset illustrated in FIG.27D is a touch panel. By touching the display portion 1732 with a fingeror the like, contents displayed on the display portion 1732 can becontrolled. Further, operations such as making calls and composing mailscan be performed by touching the display portion 1002 with a finger orthe like.

The display portion 1732 has mainly three screen modes. The first modeis a display mode mainly for displaying images. The second mode is aninput mode mainly for inputting data such as text. The third mode is adisplay-and-input mode in which two modes of the display mode and theinput mode are combined.

For example, in the case of making a call or composing a mail, a textinput mode mainly for inputting text is selected for the display portion1732 so that text displayed on a screen can be inputted. In this case,it is preferable to display a keyboard or number buttons on a large areaof the screen of the display portion 1732.

By providing a detection device including a sensor for detectinginclination, such as a gyroscope or an acceleration sensor, inside themobile phone handset illustrated in FIG. 27D, data displayed on thedisplay portion 1732 can be automatically changed by determining theorientation of the mobile phone handset (whether the mobile phonehandset is placed horizontally or vertically).

Further, the screen modes are changed by touching the display portion1732 or operating the operation button 1737 of the housing 1731.Alternatively, the screen modes may be changed depending on the kind ofan image displayed on the display portion 1732. For example, when asignal of an image displayed on the display portion is moving imagedata, the screen mode can be changed into the display mode. When thesignal is text data, the screen mode can be changed into the input mode.

Further, in the input mode, when input by touching the display portion1732 is not performed for a certain period while a signal detected by anoptical sensor in the display portion 1732 is detected, the screen modemay be controlled so as to be changed from the input mode into thedisplay mode.

The display portion 1732 can also function as an image sensor. Forexample, the image of a palm print, a fingerprint, or the like is takenby an image sensor by touching the display portion 1732 with the palm orthe finger, so that authentication can be performed. Further, by using abacklight which emits near-infrared light or a sensing light sourcewhich emits near-infrared light in the display portion, the image of afinger vein, a palm vein, or the like can be taken.

In this embodiment, examples of electronic devices each including thedisplay device described in any of the above embodiments are described.The electronic devices each include a display device in which the shiftregister in Embodiment 1 or 2 is mounted on a driver circuit. In thecase where a microcrystalline semiconductor is used for a channel regionof a thin film transistor included in the shift register, an increase inthe size of the display device, a reduction in cost, an improvement inyield, or the like can be achieved. Further, by the use of amicrocrystalline semiconductor for the channel region of the thin filmtransistor, degradation of characteristics of the thin film transistorcan be suppressed, so that the life of the display device can beextended.

Note that the contents described in each drawing in this embodiment canbe freely combined with or replaced with the contents described in anyof the other embodiments as appropriate.

This application is based on Japanese Patent Application serial no.2009-029477 filed with Japan Patent Office on Feb. 12, 2009, the entirecontents of which are hereby incorporated by reference.

1. (canceled)
 2. A display device comprising: a shift registercomprising: a first transistor; a second transistor; a third transistor;a fourth transistor; a fifth transistor; a sixth transistor; a seventhtransistor; an eighth transistor; a ninth transistor; a tenthtransistor; an eleventh transistor; a twelfth transistor; a thirteenthtransistor; and a fourteenth transistor, wherein one of a source and adrain of the first transistor is electrically connected to one of asource and a drain of the second transistor, wherein one of a source anda drain of the third transistor is electrically connected to one of asource and a drain of the fourth transistor, wherein the one of thesource and the drain of the third transistor is electrically connectedto a gate of the first transistor, wherein one of a source and a drainof the fifth transistor is electrically connected to one of a source anda drain of the sixth transistor, wherein the one of the source and thedrain of the fifth transistor is electrically connected to one of asource and a drain of the seventh transistor, wherein the one of thesource and the drain of the fifth transistor is electrically connectedto a gate of the second transistor, wherein the one of the source andthe drain of the fifth transistor is electrically connected to a gate ofthe fourth transistor, wherein one of a source and a drain of the eighthtransistor is electrically connected to one of a source and a drain ofthe ninth transistor, wherein one of a source and a drain of the tenthtransistor is electrically connected to one of a source and a drain ofthe eleventh transistor, wherein the one of the source and the drain ofthe tenth transistor is electrically connected to a gate of the eighthtransistor, wherein one of a source and a drain of the twelfthtransistor is electrically connected to one of a source and a drain ofthe thirteenth transistor, wherein the one of the source and the drainof the twelfth transistor is electrically connected to one of a sourceand a drain of the fourteenth transistor, wherein the one of the sourceand the drain of the twelfth transistor is electrically connected to agate of the ninth transistor, wherein the one of the source and thedrain of the twelfth transistor is electrically connected to a gate ofthe eleventh transistor, wherein the one of the source and the drain ofthe first transistor is electrically connected to a gate of the tenthtransistor, wherein the other of the source and the drain of the firsttransistor is electrically connected to a first wiring, wherein theother of the source and the drain of the eighth transistor iselectrically connected to a second wiring, wherein the other of thesource and the drain of the second transistor is electrically connectedto a third wiring, wherein the other of the source and the drain of thefourth transistor is electrically connected to the third wiring, whereinthe other of the source and the drain of the sixth transistor iselectrically connected to the third wiring, wherein the other of thesource and the drain of the ninth transistor is electrically connectedto the third wiring, wherein the other of the source and the drain ofthe eleventh transistor is electrically connected to the third wiring,wherein the other of the source and the drain of the thirteenthtransistor is electrically connected to the third wiring, wherein a gateof the seventh transistor is electrically connected to a fourth wiring,and wherein a gate of the fourteenth transistor is electricallyconnected to the fourth wiring.
 3. The display device according to claim2, wherein the shift register further comprises a fifteenth transistor,a sixteenth transistor, a seventeenth transistor, an eighteenthtransistor, a nineteenth transistor, a twentieth transistor and atwenty-first transistor, wherein one of a source and a drain of thefifteenth transistor is electrically connected to one of a source and adrain of the sixteenth transistor, wherein one of a source and a drainof the seventeenth transistor is electrically connected to one of asource and a drain of the eighteenth transistor, wherein the one of thesource and the drain of the seventeenth transistor is electricallyconnected to a gate of the fifteenth transistor, wherein one of a sourceand a drain of the nineteenth transistor is electrically connected toone of a source and a drain of the twentieth transistor, wherein the oneof the source and the drain of the nineteenth transistor is electricallyconnected to one of a source and a drain of the twenty-first transistor,wherein the one of the source and the drain of the nineteenth transistoris electrically connected to a gate of the sixteenth transistor, whereinthe one of the source and the drain of the nineteenth transistor iselectrically connected to a gate of the eighteenth transistor, whereinthe one of the source and the drain of the eighth transistor iselectrically connected to a gate of the seventeenth transistor, whereinthe other of the source and the drain of the fifteenth transistor iselectrically connected to the first wiring, wherein the other of thesource and the drain of the sixteenth transistor is electricallyconnected to the third wiring, wherein the other of the source and thedrain of the eighteenth transistor is electrically connected to thethird wiring, wherein the other of the source and the drain of thetwentieth transistor is electrically connected to the third wiring, andwherein a gate of the twenty-first transistor is electrically connectedto the fourth wiring.
 4. A display device comprising: a shift registercomprising: a first transistor; a second transistor; a third transistor;a fourth transistor; a fifth transistor; a sixth transistor; a seventhtransistor; an eighth transistor; a ninth transistor; a tenthtransistor; an eleventh transistor; a twelfth transistor; a thirteenthtransistor; and a fourteenth transistor, wherein one of a source and adrain of the first transistor is electrically connected to one of asource and a drain of the second transistor, wherein one of a source anda drain of the third transistor is electrically connected to one of asource and a drain of the fourth transistor, wherein the one of thesource and the drain of the third transistor is electrically connectedto a gate of the first transistor, wherein one of a source and a drainof the fifth transistor is electrically connected to one of a source anda drain of the sixth transistor, wherein the one of the source and thedrain of the fifth transistor is electrically connected to one of asource and a drain of the seventh transistor, wherein the one of thesource and the drain of the fifth transistor is electrically connectedto a gate of the second transistor, wherein the one of the source andthe drain of the fifth transistor is electrically connected to a gate ofthe fourth transistor, wherein one of a source and a drain of the eighthtransistor is electrically connected to one of a source and a drain ofthe ninth transistor, wherein one of a source and a drain of the tenthtransistor is electrically connected to one of a source and a drain ofthe eleventh transistor, wherein the one of the source and the drain ofthe tenth transistor is electrically connected to a gate of the eighthtransistor, wherein one of a source and a drain of the twelfthtransistor is electrically connected to one of a source and a drain ofthe thirteenth transistor, wherein the one of the source and the drainof the twelfth transistor is electrically connected to one of a sourceand a drain of the fourteenth transistor, wherein the one of the sourceand the drain of the twelfth transistor is electrically connected to agate of the ninth transistor, wherein the one of the source and thedrain of the twelfth transistor is electrically connected to a gate ofthe eleventh transistor, wherein the one of the source and the drain ofthe first transistor is electrically connected to a gate of the tenthtransistor, wherein the other of the source and the drain of the firsttransistor is electrically connected to a first wiring, wherein theother of the source and the drain of the eighth transistor iselectrically connected to a second wiring, wherein the other of thesource and the drain of the second transistor is electrically connectedto a third wiring, wherein the other of the source and the drain of thefourth transistor is electrically connected to the third wiring, whereinthe other of the source and the drain of the sixth transistor iselectrically connected to the third wiring, wherein the other of thesource and the drain of the ninth transistor is electrically connectedto the third wiring, wherein the other of the source and the drain ofthe eleventh transistor is electrically connected to the third wiring,wherein the other of the source and the drain of the thirteenthtransistor is electrically connected to the third wiring, wherein a gateof the seventh transistor is electrically connected to a fourth wiring,wherein a gate of the fourteenth transistor is electrically connected tothe fourth wiring, wherein the one of the source and the drain of thefirst transistor is electrically connected to i-th (i is a naturalnumber) row gate line, and wherein the one of the source and the drainof the eighth transistor is electrically connected to i+2-th row gateline.
 5. The display device according to claim 4, wherein the shiftregister further comprises a fifteenth transistor, a sixteenthtransistor, a seventeenth transistor, an eighteenth transistor, anineteenth transistor, a twentieth transistor and a twenty-firsttransistor, wherein one of a source and a drain of the fifteenthtransistor is electrically connected to one of a source and a drain ofthe sixteenth transistor, wherein one of a source and a drain of theseventeenth transistor is electrically connected to one of a source anda drain of the eighteenth transistor, wherein the one of the source andthe drain of the seventeenth transistor is electrically connected to agate of the fifteenth transistor, wherein one of a source and a drain ofthe nineteenth transistor is electrically connected to one of a sourceand a drain of the twentieth transistor, wherein the one of the sourceand the drain of the nineteenth transistor is electrically connected toone of a source and a drain of the twenty-first transistor, wherein theone of the source and the drain of the nineteenth transistor iselectrically connected to a gate of the sixteenth transistor, whereinthe one of the source and the drain of the nineteenth transistor iselectrically connected to a gate of the eighteenth transistor, whereinthe one of the source and the drain of the eighth transistor iselectrically connected to a gate of the seventeenth transistor, whereinthe other of the source and the drain of the fifteenth transistor iselectrically connected to the first wiring, wherein the other of thesource and the drain of the sixteenth transistor is electricallyconnected to the third wiring, wherein the other of the source and thedrain of the eighteenth transistor is electrically connected to thethird wiring, wherein the other of the source and the drain of thetwentieth transistor is electrically connected to the third wiring, andwherein a gate of the twenty-first transistor is electrically connectedto the fourth wiring.
 6. A display device comprising: a shift registercomprising: a first transistor; a second transistor; a third transistor;a fourth transistor; a fifth transistor; a sixth transistor; and aseventh transistor, wherein one of a source and a drain of the firsttransistor is electrically connected to a first wiring, wherein theother of the source and the drain of the first transistor iselectrically connected to a second wiring, wherein one of a source and adrain of the second transistor is electrically connected to a thirdwiring, wherein the other of the source and the drain of the secondtransistor is electrically connected to the second wiring, wherein oneof a source and a drain of the third transistor is electricallyconnected to the first wiring, wherein the other of the source and thedrain of the third transistor is electrically connected to a fourthwiring, wherein a gate of the third transistor is electrically connectedto a gate of the first transistor, wherein one of a source and a drainof the fourth transistor is electrically connected to the gate of thefirst transistor, wherein a gate of the fourth transistor iselectrically connected to a fifth wiring, wherein one of a source and adrain of the fifth transistor is electrically connected to the thirdwiring, wherein the other of the source and the drain of the fifthtransistor is electrically connected to the gate of the firsttransistor, wherein a gate of the fifth transistor is electricallyconnected to a gate of the second transistor, wherein one of a sourceand a drain of the sixth transistor is electrically connected to thethird wiring, wherein the other of the source and the drain of the sixthtransistor is electrically connected to the gate of the secondtransistor, wherein a gate of the sixth transistor is electricallyconnected to the fifth wiring, wherein one of a source and a drain ofthe seventh transistor is electrically connected to the gate of thesecond transistor, and wherein a gate of the seventh transistor iselectrically connected to the second wiring.